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Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.

Should the rest of the bits in the virtual address (12 bits) be generally considered as the block size of a cache line ?

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Assuming this is a direct-mapped cache, \$20\$ bits are reserved for tag. It means \$32-20=12\$ bits are reserved for index + offset.

There are \$1024=2^{10}\$ cache lines, which means \$10\$ bits are needed to select a cache line ie., index = \$10\$ bits. The remaining \$12-10=2\$ bits should be for offset then. i.e., the cache-block/cache-line size = \$2^2 = 4\$ bytes = \$32\$ bits.

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