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For a D flip flop with an asynchronous reset, what is the behavior if the reset input signal is synchronized with the input clock?

This is what I'm picturing: enter image description here If the CLR signal is just a divided version of the CLK input, will the output ever change? I drew a possible output - what is the correct output? ~Q will only go low when CLR is high and CLK is on a positive transition.

The first output I drew for ~Q is what I think it would be for ideal, zero delay flip flops. In this case, CLR and ~Q would change on the same clock edge.

The second output I drew for ~Q is what I think it would be for non-ideal flip-flops. For even larger delays, I think ~Q would never go low.

What is the correct output for ~Q in this case? I'm using a similar circuit for re-timing a clock signal, where the CLR input will be synchronized to the CLK input.

EDIT: cropped image to remove an incorrect output I drew.

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  • \$\begingroup\$ you are overthinking this ... the behavior is the same ... the reset is asynchronous ... when the reset signal is asserted, then the FF resets ... maybe I am not understanding what your question actually is \$\endgroup\$
    – jsotola
    Jun 30, 2021 at 23:27
  • \$\begingroup\$ Maybe so... I'm thinking that if there is any delay in the first flip flop, the CLR signal will stay low until the CLK rising edge is complete. If that happens, the output won't change on that clock signal. On the next CLK rising edge, CLR goes low again, and the output is forced high. So I'm thinking that any delay in the flip-flops would cause the output to be fixed. \$\endgroup\$
    – hucklord
    Jun 30, 2021 at 23:40
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    \$\begingroup\$ @hucklord Hold time and Setup time (more accurately called Removal and Recovery time in asynchronous signals context) have to be met for the De-assertion of the CLR signal. Assertion has no timing requirements. \$\endgroup\$
    – Mitu Raj
    Jul 1, 2021 at 7:35

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The CLR signal is not just a divided version of the clock...it is also delayed after the clock. If the delay from clock-to-Q for the bottom flip-flop is less than the CLR input hold time of the top flip-flop then the behavior is unpredictable.

Assuming that the clock-to-Q is greater than the CLR hold time, then the CLR will clear the top flip-flop shortly after the clock edge. You will see short "runt" high pulses from the top flip-flop.

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    \$\begingroup\$ I don't understand your first comment, about the minimum clock-to-Q delay. I see problems when this delay is less than the rise time of the CLK signal, but I don't see how the CLR hold time is relevant. What you said about the runt pulses makes sense! They would appear on the CLK rising edges when CLR is high. Thanks for the response! \$\endgroup\$
    – hucklord
    Jun 30, 2021 at 23:53
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    \$\begingroup\$ @ShashankVM "if the hold time...is not met, the flip-flop won't be reset" No, this is not correct. If the hold time is not met then the flip-flop state is unpredictable. The flip-flop can even become metastable. It can have an output voltage that is neither a valid logic '1' nor a valid logic '0'. This is likely to cause havoc in whatever logic uses the output of this flip-flop. \$\endgroup\$ Jul 7, 2021 at 13:52
  • \$\begingroup\$ Yes you are right. It becomes metastable \$\endgroup\$ Jul 7, 2021 at 13:53

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