For a D flip flop with an asynchronous reset, what is the behavior if the reset input signal is synchronized with the input clock?
This is what I'm picturing: If the CLR signal is just a divided version of the CLK input, will the output ever change? I drew a possible output - what is the correct output? ~Q will only go low when CLR is high and CLK is on a positive transition.
The first output I drew for ~Q is what I think it would be for ideal, zero delay flip flops. In this case, CLR and ~Q would change on the same clock edge.
The second output I drew for ~Q is what I think it would be for non-ideal flip-flops. For even larger delays, I think ~Q would never go low.
What is the correct output for ~Q in this case? I'm using a similar circuit for re-timing a clock signal, where the CLR input will be synchronized to the CLK input.
EDIT: cropped image to remove an incorrect output I drew.