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I am desigining a 4-layer PCB with the following stack-up: Signal Top, Ground Plane, Power Plane, Signal Bottom.

This is the first PCB I make like this, which includes a noisy SMPS with a switching frequency of 600KHz, as well as a 32MHz uC and a wireless 2.4GHz module. I wish to isolate the noise of the different blocks and prevent it from interfering in another block, for example, the SMPS and uC noises should not interfere with the wireless module. For that, I am splitting the power plane in three closed areas, one for each voltage (SMPS' generated 5.0V and 3.3V and 5.0V from a very small 50mA linear regulator for the auxiliary turn-on system), but keep the ground plane unsplitted and covering all of the board. The SMPS, the uC and the wireless module blocks are separated from each other's on the board.

The questions are:

  1. This split up arrangement would help from noise traveling between the modules?
  2. Would pouring up ground copper in the top and bottom sides help reduce EMI noise external to the board?
  3. Would be better to also split up the ground plane (and NO ground pouring on top and bottom sides to avoid a loop), and connect it in a star fashion? I heard that is better to keep the ground plane whole, but everyone seems to have his own version.

My understanding is that a ground place should always be below or above the signal and power traces to minimize loops and reduce EMI generated by the board. Also, IF the different blocks are already physically separated on the board, their return currents would flow in the unsplitted ground plane without interfering with each other. Is that correct? But I also read about splitting the ground plane into zones, one for each subsytem and connecting these different blocks in only one point (star connection). Which is better, and why?

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    \$\begingroup\$ Let me remind one thing. The first rule for face EMC problems is: Decrease the source of noise. Have you tried to decrease the frequency of your SMPS? Have you added a snubber in the switching-node? The layout of SMPS is properly? How about the decoupling for uC? All these points decrease the noise in you circuit. \$\endgroup\$ – Jesus Castane Feb 8 '13 at 7:12
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    \$\begingroup\$ Yes I considered the SMPS frequency and I am using the right one for this application. There is a requirement for one of the components on the board that if a SMPS is used, its frequency should be greater than 500KHz to avoid harmonic interference. I chose 600KHz because increasing it too much (the limit is about 2.2MHz) reduces the SMPS efficiency. At 600KHz, its efficiency is about 85%, quite good while also complying with the previous requirement. \$\endgroup\$ – Reuven Feb 9 '13 at 3:19
  • \$\begingroup\$ @Jesús I considered the PS frequency and am using the right one for the application. There is a requirement for one comp. on the board that if a SMPS is used, its frequency should be greater than 500KHz to avoid harmonic interference. 600KHz is ok because increasing more reduces the PS efficiency. At 600KHz its efficiency of 85% is quite good. The PS generates two voltages, +5.0V and +3.3V, so am using two versions of the LT3970 for each output and each has its own split on the power plane + the unsplitted ground plane underneath. The uC has decoupling in every Vdd and its own power plane. \$\endgroup\$ – Reuven Feb 9 '13 at 3:51
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This split up arrangement would help from noise traveling between the modules?

If you have multiple power voltages and a 4-layer board you don't have much choice. You have to deliver different voltages to the different loads. Whether it reduces or increases noise has a lot to do with the details of how you lay it out, it's not possible to just give a blanket answer to this question. Better to look at it as, you have to split your power plane --- what's the best way to do that?

Would pouring up ground copper in the top and bottom sides help reduce EMI noise external to the board?

It can, if you provide multiple vias to connect the outer layer ground area to the ground plane. It will also make your fab vendor happy because it will reduce the amount of copper they have to etch to make your board.

Be careful of bringing the outer-layer ground too close to your 2.4 GHz traces because if it's closer than, say, 5 tracewidths it will change the characteristic impedance of your controlled-impedance line.

Would be better to also split up the ground plane (and NO ground pouring on top and bottom sides to avoid a loop), and connect it in a star fashion? I heard that is better to keep the ground plane whole, but everyone seems to have his own version.

Short answer: no.

If you pay special attention to how you split up the power plane, and if your circuit demands it, then there are cases where it can improve things.

But if you want a single answer from somebody who knows almost nothing about the circuit you're designing, then the best answer is not to split the ground plane.

One more thing to watch for

Your stack up is signal-ground-power-signal. With splits in the power plane.

When you route on the bottom layer, try not to cross the splits in the power plane, because those bottom layer traces will actually be using the power net, not ground, as the return path for high-frequency components of the signal.

Also, be careful of (high-speed) signals jumping from top to bottom layer, because this will also require a transition of the return current from the power net to the ground net. This return current will probably pass through the nearest decoupling capacitor --- so the second best thing is to put a decoupling capacitor near each place where return current needs to cross between planes. (Best thing is not cross between planes at all).

Edit

I am making sure all the HF signals don't cross splits, but there are a few DC tracks which unavoidably cross them. Can that be a problem?

Think about this: when you say it's a dc track, do you mean the voltage doesn't change or the current doesn't change? Current changes are what causes problems with running over a split. (Voltage changes are problem only because they usually cause current changes)

So it depends if you're talking about a "dc" signal like an enable line for a power supply that's turned on once at start-up and then left at the same voltage forever, or a power track for some extra rail that wasn't worth making a split for.

A DC control signal will be no problem.

If it's a power signal with a varying load current, you can fix the problem with decoupling capacitors. A decoupling capacitor allows the high-frequency changes of the current to come through the short path through the capacitor instead of the long path through the track.

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  • \$\begingroup\$ "Better to look at it as, you have to split your power plane --- what's the best way to do that?" \$\endgroup\$ – Reuven Feb 9 '13 at 3:55
  • \$\begingroup\$ "Better to look at it as, you have to split your power plane --- what's the best way to do that?" I am making sure all the HF signals don't cross splits, but there are a few DC tracks which unavoidably cross them. Can that be a problem? Thanks for your valuable answer. \$\endgroup\$ – Reuven Feb 9 '13 at 4:09

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