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I read a lot about IBIS. "What I understood is that they basically model the input and output voltage and current data based on actual performance instead of describing them through equations like in SPICE. Please correct me if I am wrong.

I cannot for the life of me understand where they are used.

It is said to be supported by 'virtually any simulation software', but LTspice and TINA don't support it. Then I come across posts like these which say it does not work like a SPICE model.

What exactly do they do? Can I connect, say, resistors around an IBIS model of an op-amp in non-inverting configuration and expect to see an amplification? Do I need to convert it to SPICE? I am very confused.

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    \$\begingroup\$ See this. \$\endgroup\$ Jul 2, 2021 at 15:11
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    \$\begingroup\$ IBIS models are more usually used for the IO behaviour of digital parts. \$\endgroup\$ Jul 2, 2021 at 15:12
  • \$\begingroup\$ @aconcernedcitizen The link is broken. Could you please relink? \$\endgroup\$
    – pfabri
    Jan 11 at 10:06
  • \$\begingroup\$ @pfabri Unfortunately I'm not the one maintaining the link, bu tit was a document about how to use IBIS. The selected answer below does a better job. \$\endgroup\$ Jan 11 at 20:41
  • \$\begingroup\$ @aconcernedcitizen Thank you. It’s good to know that the answer below is more useful. In this case the link is probably irrelevant. \$\endgroup\$
    – pfabri
    Jan 11 at 22:07

4 Answers 4

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The main point of IBIS is to see how your digital ICs interface with analog circuitry external to those chips. Physical properties such as drive strength, pin leakage, and package parasitics can be vital in certain designs. IBIS is frequently used with PCB layout packages to validate signal integrity against the specifics of your copper traces, pours, substrates, etc. The main thing to understand about IBIS is its simplified input and output structures (see Analog Devices AN-715 AppNote), which are duplicated below: enter image description here


enter image description here


One of the most useful applications of IBIS (in my opinion) is to use the I/V data of GPOs to calculate a Thevenin equivalent source resistance for the driver pin. Then you can easily plug a voltage source and resistor to interface with your remaining analog circuity in SPICE, or simply use that resistance value for hand calculations. There are tools/software e.g. SPISim_IBIS which can directly convert the IBIS I/V curves to behavioral SPICE I/V curves, but it's slower and not as straightforward if you want to work out some things by hand. There's also a difference between ramp data and waveform data, and some free tools only let you use one of them.

I give an example below, so you can see for yourself. Something like this can be useful when interfacing digital outputs with gain circuits (think op amp or resistive DAC). You don't want to get burned by assuming an output pin's resistance is equivalent to 0Ω or something else. I prefer doing this calculation using my own lab measurements, but if I don't have hardware available (or I'm too lazy) I'll do it using the IBIS data.

STM32 microcontrollers seem to be popular lately from what I hear, so I'll use the stm32g030_031_041_so8n.ibs file found on ST's website. This is the file for the SO8N package version of the STM32G030. I'm going to work with the following model found in the file, which includes a description of the specific configuration for this type of I/O pin:

io6_ft_3v3_mediumspeed  "GPIO-3.3V range - medium speed"

If you scroll or search for this model in the text, you will eventually see where it starts which looks like this:

|************************************************************************
|                    Model io6_ft_3v3_mediumspeed
|************************************************************************
|  
[Model]  io6_ft_3v3_mediumspeed
Model_type I/O
Polarity       Non-Inverting
Enable        Active-Low
Vinl =   0.990000V
Vinh =   2.310000V
Vmeas =  1.650000V
Cref =   30.000000pF
Rref =   100.000000M
Vref =   0.0V
C_comp    1.290400pF        1.272500pF          1.305600pF

Scroll down a little further to where it says this:

[Rising Waveform] 
R_fixture= 50.000000
V_fixture= 0.0
V_fixture_min= 0.0
V_fixture_max= 0.0

which means that this is Rising Waveform data when the output pin is connected to 0V via a 50Ω load. The idea is to analyze the ON state of the PMOS (top) transistor of the output structure.

If we scroll to the end of the time series data for that section we see something like this:

|time             V(typ)            V(min)              V(max)
|
...
...
...
29.949950nS       1.783884V         1.600996V           1.892836V
31.471471nS       1.788090V         1.602697V           1.901179V
31.631632nS       1.788290V         1.602898V           1.901984V
33.793794nS       1.791394V         1.605099V           1.910528V
34.914915nS       1.793096V         1.605499V           1.913845V
36.276276nS       1.794097V         1.605999V           1.917766V
39.879880nS       1.796100V         1.607300V           1.924400V

The last row is where they determined the output settled after fully switching from low to high. Another way to look at this is: when the pin is set high and you connect it to a 50Ω load to ground, there will be 1.796V (typically) at the pin. We can use the following formula to calculate the Thevenin equivalent resistance of the output pin:

$$ \begin{align*} R_{\text{th(high)}} &= R_{\text{load}} \cdot \Big( \frac{V_{DD}}{V_{\text{load}}}-1 \Big) \\~\\ R_{\text{th(high)}} &= 50 \cdot \Big( \frac{3.3}{1.796}-1 \Big) \\~\\ R_{\text{th(high)}} &\approx 41.871 \Omega \end{align*} $$

If your external circuitry is only sensitive to when the pin is being driven high, then you should be fine with the above value. If not, then we can't assume the two transistors are exactly symmetric so let's do the same for the...

[Falling Waveform] 
R_fixture= 50.000000
V_fixture= 3.300000
V_fixture_min= 3.000000
V_fixture_max= 3.600000

Notice how we're using the batch of values for when V_fixture is 3.3 V (there's another data set for 0 V, so be aware!). This means that the 50 Ω load is now connected to 3.3 V so we can analyze the ON state of the NMOS (bottom) transistor.

|time             V(typ)            V(min)              V(max)
|
...
...
...
29.789790nS       1.589774V         1.421969V           1.901713V
30.830831nS       1.586260V         1.418657V           1.898195V
31.551552nS       1.584452V         1.416348V           1.895882V
34.754755nS       1.577525V         1.409723V           1.887940V
35.075075nS       1.576922V         1.409121V           1.887438V
35.315315nS       1.576621V         1.408619V           1.886935V
39.879880nS       1.571300V         1.403500V           1.880300V

The formula is similar but slightly different (don't forget that exponent!):

$$ \begin{align*} R_{\text{th(low)}} &= R_{\text{load}} \cdot \Big( \frac{V_{DD}}{V_{\text{load}}}-1 \Big)^{-1} \\~\\ R_{\text{th(low)}} &= 50 \cdot \Big( \frac{3.3}{1.571}-1 \Big)^{-1} \\~\\ R_{\text{th(low)}} &\approx 45.431 \Omega \end{align*} $$

You can use each resistance to build an output model using two voltage controlled switches with those two ON resistances, but a simpler approach would be to average the two resistances into one and use the result along with a simple independent voltage source:

$$ \begin{align*} R_{\text{th(avg)}} &= \frac{R_{\text{th(high)}} + R_{\text{th(low)}}}{2} \\~\\ R_{\text{th(avg)}} &= \frac{41.871+45.431}{2} \\~\\ R_{\text{th(avg)}} &= 43.651 \Omega \end{align*} $$

One last caveat to point out is that usually the NMOS side has a lower resistance, and that didn't happen in this example. It could be because the time data ended without it fully settling to the final value...or it could be something else. This is one reason why I like doing my own measurements (calculations/formulas are the same), but hopefully this highlights a useful application of the IBIS model data.

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IBIS models are commonly used in SI (Signal Integrity) modeling tools, like Mentor Graphics Hyperlynx. Like Peter Smith said, they basically just model the input and output characteristics of a part. I have never come across an IBIS file that said anything about the internal workings of a part.

So no, you cannot connect resistors around a IBIS model of an opamp and expect any meaningful results.

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  • \$\begingroup\$ But input and output characteristics will differ depending on connection right? Like, if I consider a non-inverting opamp for example, output will depend on gain. \$\endgroup\$ Jul 2, 2021 at 17:40
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    \$\begingroup\$ @needbrainscratched No, he means that the IBIS of an opamp (hypothetical since I've never seen one) would only contain information about the pins interfacing to the outside world, and independently at that. The rest of the insides of the chip aren't modeled, and there is no notion of how the two inputs would even path their way to the output or to each other. Everything else inside the chip is blank. Because an opamp typically needs closed-loop feedback from output to inverting input, it cannot function because there are no diff-pairs or gain stages on the model's insides to complete the loop. \$\endgroup\$
    – Ste Kulov
    Jul 3, 2021 at 3:37
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Free Software to Simulate IBIS Models

Micro-Cap 12 by Spectrum Software is now free and capable of doing IBIS simulations. It used to retail for $4500+ so it's definitely not one to discard on a whim. You can quickly read more about the software by going through this Commercial Circuit Simulator Goes Free Hackaday article.

The Winter 2008 Newsletter - Using the IBIS Components hosted on Spectrum's own site gives an introduction to IBIS modelling, but the screenshots are broken, sadly. Looking at the page through the WayBackMachine will load screenshots properly, though.

This IBIS Output Impedance Made Easy article shows a few screenshots from the software, but lacks practical details on how to use the software.

In-Depth PDF on the Topic

An entire PDF guide titled How to Use the IBIS Model under the file name (IBIS_HowToUse.pdf) is available. This was linked to by @aconcernedcitizen above, but that link is dead.

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IIRC, Ibis models are simpler than spice models because they do not show any internal details about the process technology or the inner workings of the the I/O. So IC companies like them because their proprietary info is not disclosed.

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