I've got a board where I'm using the TI TPS63050 switching regulator. I've recently discovered that if I put a bit more load on the output, I get some spurious event on the PG (power good) open-drain output of that device, which I have used as a enable signal for the processor of my system (an ESP32 fwiw). I have been able to cause this by attaching a 47 Ohm resistor to the 3.3V output of the regulator and attaching the oscilloscope to the 3.3V output and the PG signal. As far as I can tell, I'm nowhere near the current limit of the regulator, it's cool to the touch, and the 3.3V output is pretty stable, certainly higher than 2.97V (i.e. 90% of 3.3V).

My measurement of the PG event suggests that the event lasts around 400ms perhaps with two partial pull-downs during that time period. I realize I've oversized the pull-up resistor (R11) slightly at 4.7k given that the PG output can only sink 0.1mA, but I think that just means it won't pull down all the way to GND right (i.e. it will only pull down to 0.47V)?

I'm not sure how to diagnose this further and without a root cause I don't know what to do to solve it.

Schematics of what I'm doing with the TPS63050 are below, as well as how the PG signal is routed elsewhere on my board. VCC is my input voltage which is typically in the 3.5 - 4.8V range, and VDD is the output of the TPS63050 configured for 3.3V output.

enter image description here enter image description here enter image description here

and there's one other chip, that I run the POWER_GOOD_MCU signal to connected to its N_RESET input with another 0.1uF capacitor to GND attached. It's not really implicated because whether or not that chip is populated the same problem exists.

[UPDATE] ... and here's my layout for the TPS63050. It's 4-layer, and there's a solid ground plane below the top layer, and VCC and VDD are on a split plane below that, so they are routed to by direct via drops:

enter image description here

Disconnecting R34 makes my problem go away, but I'm not in love with the idea of ignoring the PG signal at a system level.

Here also is a representative scope trace with VCC, VDD, and PG observed simultaneously whilst the PG signal freaks out briefly. Note that 3.3V (VDD) seems unperturbed during the event in question.

enter image description here

Can you suggest to me what I might be failing to measure that is giving rise to PG not staying good, or otherwise what I might be missing here?

  • \$\begingroup\$ what's the type of capacitors used on the input and output of the TPS chip? are they low ESR? or higher ESR bulk electrolytic? \$\endgroup\$
    – KyranF
    Jul 2 at 22:05
  • \$\begingroup\$ can you please capture another scope trace showing the output voltage of VCC from the regulator, and the PG output, using the PG output going < 3v as the scope trigger event, and try to get as high resolution on the X axis as you can? Also ensure you have a small scope probe inductance and distance between measured point and a 0V reference. From the X axis resolution it's 2ms/square, try to go for 200usec / square to show the event in more detail. I expect there's a very small dip < 2.9V and the PG is glitching out. the 90% falling threshold is "typical" in the datasheet. \$\endgroup\$
    – KyranF
    Jul 2 at 22:15
  • \$\begingroup\$ KyranF, they are all 47uF ceramics, which I believe qualifies as low ESR. \$\endgroup\$
    – vicatcu
    Jul 2 at 22:55
  • 2
    \$\begingroup\$ @vicatcu Why are you so fixed on the idea that it should not happen, when I gave many reasons why it could happen and suggested to check them? Quote from datasheet: "The power good goes low when the device is in under voltage lockout, in thermal shutdown or in current limit.". It can also go low if EN goes low, have you checked that? Is the inductor rated for 2.5A peaks as in examples? Most likely voltage sags too much due to insufficient output capacitance/ESR and controller tries to push current to output so much that it hits current limit. \$\endgroup\$
    – Justme
    Jul 3 at 7:54
  • 1
    \$\begingroup\$ Here's a thought... should I have tied ILM0 to VCC instead of GND? \$\endgroup\$
    – vicatcu
    Jul 3 at 20:03

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