# Why is the output not zero for zero differential input?

To start with, I am simulating a StrongARM latch. Surprisingly, the circuit is not giving a zero output for zero differential input.

In the circuit, one clock cycle is 2 ns and VDD is 1.8 V.

The MOSFET model used was BSIM3, HSPICE level 49, 180 nm technology.

Transistor sizing:

 M1,M2:  CMOSN l=0.18u w=50u ad=18e-12 as=18e-12 pd=100.72u ps=100.72u

M3,M4:  CMOSN l=0.18u w=10u ad=3.6e-12 as=3.6e-12 pd=20.72u ps=20.72u

M5,M6:  CMOSP l=0.18u w=25u ad=9e-12 as=9e-12 pd=50.72u ps=50.72u

S1-4:   CMOSP l=0.18u w=2.5u ad=0.9e-12 as=0.9e-12 pd=5.72u ps=5.72u


Would it be due to an offset, or do these models have an offset automatically - or is it some simulation error?

• Surely the output average level should be 50% of Vcc = 0.9 volts. It looks to be that but, what happens when the input voltages are exactly equal? Jul 3 at 20:05
• Shouldn't this question have more tags, like for simulation, model, MOS/MOSFET, (meta) stability, etc.? Jul 4 at 11:10
• What is the intended use? A comparator? With hysteresis? Jul 4 at 11:36
• I suggest changing the title to "Why does a metastable latch settle in simulation". Jul 4 at 12:10