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To start with, I am simulating a StrongARM latch. Surprisingly, the circuit is not giving a zero output for zero differential input.

In the circuit, one clock cycle is 2 ns and VDD is 1.8 V.

The MOSFET model used was BSIM3, HSPICE level 49, 180 nm technology.

Transistor sizing:

 M1,M2:  CMOSN l=0.18u w=50u ad=18e-12 as=18e-12 pd=100.72u ps=100.72u

 M3,M4:  CMOSN l=0.18u w=10u ad=3.6e-12 as=3.6e-12 pd=20.72u ps=20.72u

 M5,M6:  CMOSP l=0.18u w=25u ad=9e-12 as=9e-12 pd=50.72u ps=50.72u

 S1-4:   CMOSP l=0.18u w=2.5u ad=0.9e-12 as=0.9e-12 pd=5.72u ps=5.72u

Would it be due to an offset, or do these models have an offset automatically - or is it some simulation error?

Circuit

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Output SPICE model

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  • \$\begingroup\$ Surely the output average level should be 50% of Vcc = 0.9 volts. It looks to be that but, what happens when the input voltages are exactly equal? \$\endgroup\$
    – Andy aka
    Jul 3 at 20:05
  • \$\begingroup\$ Shouldn't this question have more tags, like for simulation, model, MOS/MOSFET, (meta) stability, etc.? \$\endgroup\$ Jul 4 at 11:10
  • \$\begingroup\$ What is the intended use? A comparator? With hysteresis? \$\endgroup\$ Jul 4 at 11:36
  • \$\begingroup\$ I suggest changing the title to "Why does a metastable latch settle in simulation". \$\endgroup\$
    – 7efkvNEq
    Jul 4 at 12:10
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In an ideal world, your circuit would indeed not put out any differential voltage between points X and Y because it is fully symmetrical. There are no random offsets in SPICE, it does exactly what you tell it to do. However, SPICE isn't perfect - it uses floating-point numbers and therefore necessarily has rounding errors. These rounding errors get amplified by the positive feedback loop in your circuit, causing you to get non-zero output voltage. In other words: The circuit you've built is metastable around its zero output voltage point, any kind of disturbance will cause it to fall into one of its stable states (it's a latch after all). The rounding errors of SPICE are enough to make this happen.

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