To start with, I am simulating a StrongARM latch. Surprisingly, the circuit is not giving a zero output for zero differential input.
In the circuit, one clock cycle is 2 ns and VDD is 1.8 V.
M1,M2: CMOSN l=0.18u w=50u ad=18e-12 as=18e-12 pd=100.72u ps=100.72u M3,M4: CMOSN l=0.18u w=10u ad=3.6e-12 as=3.6e-12 pd=20.72u ps=20.72u M5,M6: CMOSP l=0.18u w=25u ad=9e-12 as=9e-12 pd=50.72u ps=50.72u S1-4: CMOSP l=0.18u w=2.5u ad=0.9e-12 as=0.9e-12 pd=5.72u ps=5.72u
Would it be due to an offset, or do these models have an offset automatically - or is it some simulation error?