3
\$\begingroup\$
  • IR2113 floating channel digital-input half-bridge transformer driver
  • Dead time is properly set
  • Channel supply VPP 20-60 V, gate bias supply 15 V
  • Operation frequency 15-100 kHz, operation mode PWM or FM
  • Load type: unstable air plasma (nasty back-EMF, also EMP emission )
  • Q1 and Q2 are SiCFET, which can take a lot of abuse.

enter image description here

Problem:

  • I have burnt a tube of IR2113 on this, but I'm not sure what exactly is burning the IR2113.
  • I speculated that it was back-EMF burning the gate driver, so I added D1 and D7, but the gate driver is still burning.
  • A common approach is adding RC snubber VS to GND and VS to VPP, but I don't know what RC value to use to allow driving frequency to pass.
\$\endgroup\$
6
  • \$\begingroup\$ Are you sure that the system D1-D7-C2-C3 is ok ? I would add 2 more diodes D1 & D7 not Zener ! So (serial diode - capacitor) || another diode) \$\endgroup\$
    – Antonio51
    Jul 5, 2021 at 7:00
  • \$\begingroup\$ @Antonio51 D1 and D7 are Schottky, not Zener. They are connected anti-parallel to the caps. \$\endgroup\$
    – 7E10FC9A
    Jul 5, 2021 at 7:15
  • \$\begingroup\$ Show HO LO timing and define objective. e.g. max plasma energy or max efficiency or safe operating area or ? To understand better include Ciss or Cdg on schematic and recovery time of diodes. \$\endgroup\$ Jul 5, 2021 at 12:13
  • \$\begingroup\$ "I have burnt a tube of IR2113" A perfect summary of my master thesis. It's very layout sensitive and can not handle negative voltage even for very short times. How's your layout around it? \$\endgroup\$
    – winny
    Jul 5, 2021 at 14:04
  • \$\begingroup\$ When exactly does it fail? Does it work for a while and then blow up, or fail immediately on startup? Any chance of trying it with a predictable dummy load (a resistor would be best, if the output voltage allows) instead of the plasma bit? \$\endgroup\$
    – TooTea
    Jul 5, 2021 at 14:24

4 Answers 4

3
\$\begingroup\$

At least capacitor C6 is conneted wrong. It should be between VB and VS, as it should definitely not be on HO.

\$\endgroup\$
1
  • \$\begingroup\$ Sry, that was just a mistake in schematics, the real circuit has the bootstrap cap connected correctly. \$\endgroup\$
    – 7E10FC9A
    Jul 5, 2021 at 12:56
1
\$\begingroup\$

Add a fast-switching flywheel diode between pin 2 and 5 as you may have high transients there. Q2 has a diode but the switching time my be too slow.

\$\endgroup\$
1
  • \$\begingroup\$ I've had the same problem, and this answer proposes what fixed it. If Q1 (high side) switches off before Q2 (low side) switches on, the load inductance will pull the switching node negative. Ideally the body diode of Q2 will turn on and limit the negative voltage to less than one volt, but in practice the body diode may be too slow, allowing a larger transient. If the transient at the switching node (pin VS) exceeds -25 V (relative to pin COM) the gate driver is likely to fail. \$\endgroup\$
    – jms
    Dec 26, 2023 at 18:04
1
\$\begingroup\$

What if the core is saturating?

The first thing that my eyes caught is that the mid-point is set with capacitors (C2 and C3). This is not a good way because the capacitors have a very high tolerance. This inequality results in a mid-point shift, and this shift (i.e. offset) finally results in saturation of the core. This cannot be seen in simulation because the capacitors are taken as ideal ones.

So,

1- Place equal and high enough resistors across the divider capacitors so that they share the VPP equally.

2- Place D1 and D7 (should be fast-recovery diodes) across the MOSFETs instead (Don't trust in the MOSFETs' body diodes).

3- Place a 1uF/100V ceramic capacitor between the mid-point and the transformer's primary (pin-2 in the schematic). This blocking capacitor helps to prevent mid-point-shift-related problems.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ Thanks for answering. The core has gap so I wasn't expecting saturation. Ceramic cap will most likely overheat, I originally have a 1uF MKP there but it blocks too much low frequency in PWM mode. Can you think of a reason why the gate driver is burning ? \$\endgroup\$
    – 7E10FC9A
    Jul 5, 2021 at 13:18
  • \$\begingroup\$ The core has gap so I wasn't expecting saturation. That air gap cannot prevent the saturation caused by flux walking (Flux walking is the result of the imbalance that I mentioned in my answer). That air gap only brings a delay to the onset of flux saturation. I originally have a 1uF MKP there but it blocks too much low frequency in PWM mode so you need to check the capacitor's datasheet for a frequency vs capacitance or frequency vs rated voltage graph: If the capacitance drops too much at the switching frequency, it will chop off the switched current. \$\endgroup\$ Jul 5, 2021 at 14:43
  • \$\begingroup\$ Is there more elegant solution to balance the large caps ? Also, wouldn't connecting a 1uF in series makes the large capacitance of the cap bank useless ? \$\endgroup\$
    – 7E10FC9A
    Jul 7, 2021 at 12:02
0
\$\begingroup\$

C6 and C7 are electrolytic - their ESR is quite high above 1MHz. You must connect a ceramic capacitors on 22nF with as short as possible wires between 1) Vb, Vs; 2) Vcc, COM. I mean between power terminals of the IC.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.