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I wanted to find the short circuit current in a CMOS inverter. I read "chapter 5 ,Digital IC (Rabaey.)" When I tried to make a CMOS inverter, I am very confused about what the 'short circuit current' is. The current through the drain of the PMOS is not equal to the current through the source, same is true with NMOS. Which current is the short circuit current? In the text, the shape was approximated as a triangle.

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  • \$\begingroup\$ That's called shoot-through current not short-circuit current. \$\endgroup\$
    – Andy aka
    Commented Jul 5, 2021 at 9:32
  • \$\begingroup\$ @Andyaka Actually the heading was direct path current , but in between the paragraph it was used short circuit current. Are direct current and shoot through current same ? or short circuit current and direct path current same ? \$\endgroup\$ Commented Jul 5, 2021 at 10:18
  • \$\begingroup\$ @Andyaka When I googled shoot-through current , it said thats when Vdd tries to pull and GND tries to push at the same time. So effectively some current is used to charge the Cload(and parasitic capacitances ) while some will flow to GND ? Is this what happens in the circuit? \$\endgroup\$ Commented Jul 5, 2021 at 10:19
  • \$\begingroup\$ Shoot-through is when both MOSFETs are partially on at the same time. \$\endgroup\$
    – Andy aka
    Commented Jul 5, 2021 at 10:38
  • \$\begingroup\$ What about short circuit /direct path current ? I thought these meant there is a path between Vdd and GND which appears to be same as your explanation for shoot current. Does 'partially' make the diffence between the two? @Andyaka \$\endgroup\$ Commented Jul 5, 2021 at 10:41

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Unfortunately, all the figures have errors illustration by my simulation in the location of \$I_{SC}\$ and arrow. enter image description here For a rising input, the supply current comes from the Nch low side driver and not the high side as shown. However, initially from t=0 the high side would be the only active drive as a "big" load cap charges up.

This shoot-thru is maximum when Vin near Vdd/2 at the input threshold casing a low RdsOn for each FET to be ON at the same time between both FETs.

A large external capacitance diverts the shoot-thru current to the outside cap and increases the duration of the current pulse.
Internal Miller Capacitance is the cause of latency and simultaneous shoot thru. Beyond this time with a large load C, only one (1) driver is active, so it is not shoot-thru for that period. Increasing the load capacitance simply increases the current pulse width.

Ron for each family of logic controls current limit

CD4xxx family @ 12V RdsOn = 300 Ohm @ , @ 3V > 1kOhm
74HCxx family @ 5V RdsOn = 50 Ohms +/-25%
74ALCxx family at 3.3V = 25 ohms +/- 25%

This is why it is important to add decoupling cap. for each CMOS IC.

enter image description here

Dynamic Power consumption

In computing the power dissipation for shootthru power dissipation or "dynamic" power as it is normally called, you could compute the change in energy of the Miller Capacitance and divide by the time interval between transitions or compute V*I=P for each transition. enter image description here

updated plot to show Pavg

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  • \$\begingroup\$ I think I understood what you explained. But the current I am looking for is the current from Vdd to GND. Any current flowing through Vdd has to either go to GND or charge any capacitor right? So I wanted to know how much current will flow directly from Vdd-M1-M2-GNd. And then calculate the power dissipated due to this . @Tony \$\endgroup\$ Commented Jul 5, 2021 at 11:01
  • \$\begingroup\$ Dear Hari, Since Vt & RdsOn has a wide tolerance (25%) you can estimate with assumptions using RdsOn and time duration. But my 2nd plot computes the product of VI max For average power, you should use the PW50% pulse width. or % duty cycle @ 10MHz in this example. \$\endgroup\$ Commented Jul 5, 2021 at 11:31
  • \$\begingroup\$ It’s not what you requested but I showed the power from supply and power dissipated in each device. does it add up? \$\endgroup\$ Commented Jul 5, 2021 at 12:00
  • \$\begingroup\$ To be honest I am still confused but I appreciate you effort. I am still reading the answer you wrote @Tony \$\endgroup\$ Commented Jul 5, 2021 at 12:04
  • \$\begingroup\$ When load C exceeds Miller C on driver, the external current begins to draw more current than the shootthru current. Ic=CdV/dt depending on ESR and Ron. The cap is ideal as shown and thus lossless (on average) but causes losses on alternate switch transitions. \$\endgroup\$ Commented Jul 5, 2021 at 12:19

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