# Propagation and contamination delays with different delays for rising and falling edges

In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way:

The propagation delay $$\t_{pd}\$$ is the maximum time from when an input changes until the output or outputs reach their final value. The contamination delay $$\t_{cd}\$$ is the minimum time from when an input changes until any output starts to change its value.. . $$\t_{pd}\$$ and $$\t_{cd}\$$ may be different for many reasons, including different rising and falling delays..

So I draw from the bold text (emphasized by me) for any circuit there is only a pair of these measures values. That is to say, if a circuit has a different delays for its rising edge (transition from 0 to 1) and falling edge (transition from 1 to 0), $$\t_{pd}\$$ is about the longest between them, and $$\t_{cd}\$$ - about the shortest.

The authors show such circuit to define the critical and short paths: and then expand on the aforementioned measures by stating that taking notice of both the critical and short paths, it is true for this circuit:

$$t_{pd} = 2*t_{pdAND} + t_{pdOR}$$ $$t_{cd} = t_{cdAND}$$

Let's suppose we encounter the very case: that AND gate has different delays for its rising and falling edges. Does it mean these equations might be wrong? There is the falling edge shown in the picture. So if this edge is quicker in terms of delays, it is either nonsense to use $$\t_{pdAND}\$$ here (because it indicates the slower rising edge measure but we are talking about the falling one) or $$\t_{pd}\$$ is not relevant to the matter in hand at all (falling edge).

As I'm concerned, for these types of situation it would be reasonable to exploit two different pairs of values: one for a rising edge and another for falling one but this is out of line with the bolded author statement. What's the right way to address these possible circuit delays differences?

• The author doesn't want to go into the intricacies. Tpd could mean different things depending on the type of timing analysis for that path; the worst delay of tpd (setup analysis). Or best delay (if hold analysis). This delay will take into account both rising and falling timing arc and see which ones is the worst/best for the analysis. Jul 5, 2021 at 14:29

Yes, these equations are all wrong. They are just rough models of circuit behavior. In fact, the propagation delay will be different for different input pins of the same gate, and may also change depending on the current state of other pins, the input rise/fall time, and the loading on the gate output.

As an engineer, the question you should ask yourself is whether the equations are useful. The equations are useful because they give you a quick estimate of the worst-case propagation delay through the circuit. If you want a better estimate, there are CAD tools specifically designed for this task, which is called "static timing analysis".

Whether or not any particular model is the "right way" is for you to decide. You might begin with a crude model, and if it says that the circuit is much faster than it needs to be then you can move on to analyzing a different circuit. If the crude model says that the circuit is close to failing then you probably want to run a more accurate analysis.

As I'm concerned, for these types of situation it would be reasonable to exploit two different pairs of values: one for a rising edge and another for falling one but this is out of line with the bolded author statement.

No, the author is correct. For propagation delay, you consider the longest path, and in this case the critical path is A to N1 to N2 to Y. The author is focusing on finding the longest path, and the author is correct.

For contamination delay the shortest path is considered. Here it is D to Y.

There is no need of considering separate propagation and contamination delays for rising edge time and falling edge time. You want your design to work for both rising and falling edges, so you consider the worst case only.

Even if the falling edge delay of AND gate is greater than the rising edge delay, this delay can't be greater than the critical path delay, because gate propagation delays are much more than rising or falling edge delays. In conclusion, the critical path has more gates, so it will always have a greater delay than the shortest path, regardless of the rising/falling edge delay of the shortest path.

$$\t_{pd}\$$ and $$\t_{cd}\$$ may be different for many reasons, including different rising and falling delays.

This is true when computing the propagation and contamination delays of a gate. When computing propagation delay, if the rising edge propagation delay is greater than the falling edge propagation delay, then the propagation delay is the rising edge propagation delay. In this case, the contamination delay will be the falling edge contamination delay.

## solution

• Use a sync Flip Flop or include opposite phase of clock in the gates

• to avoid glitches from metastable (race) conditions on output logic.