I'm making a POV (persistance of vision) display-type PCB (this is my first PCB ever), using AD9833 chips as controllable clock generators for some PWM drivers I'm using so that I can control the frequency of the PWM precisely. I'm now doing the layout on my first real attempt at this PCB and I'm worried about interference. I'm not 100% sure of what I'm doing, but looking up tips for PCB layout consistently mentions separating Analog/Digital signals. I guess technically the AD9833 is not really 'analog' as I'm using it as a digital clock generator, so am I safe placing the modules like in the layout below? The pins they use will be sort of like stand-offs, will that affect it at all?

Mainly I'm worried switching from the LEDs (max 20 kHz, likely much less) might be an issue since they're so close, but I also know that board space is important and moving the AD9833s to their own separate space would really lengthen the SPI and other connections between each which I've also read is undesirable. I have a solid ground plane between the front and back of the board, if I just flips the AD9833s and solder them to the back, would that protect it from EMI from the LED drivers? Any hints or wisdom would be really appreciated!

Updated Design (#2)


  • Added additional decoupling capacitors by LEDs and ICs (C11-C35)
  • Added a decoupling capacitor next to the 6V in (C27)
  • Removed unnecessary Teensy pins (15-19 and 34-44)
  • Remove SPI SOUT connection from U3 to avoid conflict
  • Routed SPI and other signals
  • Moved AD9833s closer to Teensy
  • Flipped AD9833s onto the rear of the board
  • Moved NRF24L01 to the East of Teensy
  • Changed NRF24L01 footprint so mounting placement is visible
  • Updated Hall Effect Sensor Footprint to allow for mounting on either side of the board


  • Add LM321 Op-Amps with 5.5 Gain to increase AD9833 output voltage (0.6V -> 3.3V)

PCB Layout Update #2

Power Plane View

Power Plane Layer of PCB

Updated Schematic (#2)

  • Updated/added parts as listed above with new symbols where required

Circuit Schematic Update #2

Current (Old) Design

Front PCB Layout

Current (Old) Schematic

Circuit Schematic


I'm using a 4-layer board with the two inner layers, one for positive voltages and the other for ground. I'm not sure if that's relevant so I've omitted it for clarity in the picture but I can add that back if needed.

  • \$\begingroup\$ As often happens for PCB reviews, the comment chain has exceeded what is reasonable for comments. Therefore it has been moved to chat and should be continued there (link below). --- As this bulk moving of comments to chat can only be done once, any further comments posted here which try to discuss the question, might be deleted without notice. Keep it in chat, please! If someone gets enough information from the chat to post an answer, then please do that. Any factual updates to the question which are decided during the chat, should be made via an edit to the question. Thanks. \$\endgroup\$
    – SamGibson
    Commented Jul 8, 2021 at 18:09
  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$
    – SamGibson
    Commented Jul 8, 2021 at 18:09

2 Answers 2


PLACEMENT and ROUTING Feedback: overall, most component placement is already very good --

  1. suggest use north half of board for processor and oscillators, middle for PWM drivers, and southmost LEDs (5V only) -- basically existing placement is very good, except I suggest move AD9833 oscillator modules further north but keep the pairings of oscillator to PWM chips (U4 closest to U1, U5 closest to U2, U6 closest to U3).

  2. create a separate fill (pour) area on the power layer along south edge of board from the +5V regulator output to the LEDs power inputs. This 5V path is the one that will have the highest currents and may be noisy if using variable brightness with PWM switching pulses. Suggest allocate about 1/3 to 1/4 of the board area on 5V power layer for only the LEDs. Put 3.3V fill in center, and another +5V fill to Teensy input along north of PCB.

  3. I do NOT recommend to split the grounds or the ground plane on this design (no separate AGND is needed). Design doesn't have any truly sensitive analog circuits on the main board to be concerned about. I recommend just keep one full PCB layer dedicated to ground as OP mentioned. Isolating the +5V power fill supplying the LEDs (comment #2) will automatically keep any high-frequency ground return currents at switching harmonics on the south half of the board (path of least inductance). The low-side switch turn on/off rate of the TLC59482 is already slow enough (30ns typical on OUTn per datasheet) that LED switching transients should not be an significant concern in a good layout.

  4. lower priority, suggest move J1 and RF module to east of the Teensy module (RF module would be best isolated from rest of circuits and doesn't use 5V).

  5. As OP described, a 4-layer PCB design will allow easy routing of this design with round/power planes to minimize EMI concerns plus provide good power and signal integrity for robust design. Recommended stackup: L1 component & traces, L2 ground, L3 split power, L4 traces. Route all clocks on Layer 1 (adjacent to Ground plane) as much as possible (route first after power & ground), for best signal integrity. High fanout clocks (SCLK) should route as roughly symmetric tree. See schematic comment #11 below as well regarding clocks.

  6. As was mentioned in by Drew in comments, decoupling caps should be added for the other on-board components such as U8 (place 0.1uF near VCC and Ground pins, similar to what was done for U4,U5,U6 ), and it would be good to have larger caps in area near the connectors for the modules RF, Teensy, and Oscillator (if kept), although the modules themselves are likely to have small capacitors closest to their chips. I'd move the 1.0uF caps C2,C4,C6 away from U4,U5,U6 and instead place spread them out -- one near J1 on 3.3V, one near Teensy U7 pin 33 (+5V input), and last near oscillator module 3.3V input (add two more 1.0uF if keeping all three oscillators). In general, smallest caps (0.1uF) in smallest packages should be placed closest to high-speed digital ASIC load pins as was done at U4,U5,U6. Larger caps (1.0uF) in larger packages place further from digital ASIC loads, working way back to largest bulk caps (47uF) placed around the source (U9 for 5V). Teensy U7 pin 31 is the +3.3V source, and would recommend a 4.7uF cap on the +3.3V power fill between that pin and rest of 3.3V loads. Likely there is a bulk cap on that pin already on the Teensy module (didn't have time to look up details of Teensy module). Also recommend adding a 10uF cap placed adjacent to +6V input pin to U9 regulator.

SCHEMATIC FEEDBACK: Some significant concerns to investigate... 7. the AD9833 is an expensive, precision, numerically controlled ANALOG oscillator, for applications requiring a precision variable frequency signal for analog sensing applications. The raw output from this chip VOUT is only 0V to 0.6V (low voltage analog) and is not compatible for a direct connection to GSCLK input pin of TLC59482, which requires 0V to VCC (3.3V) signal swing for input (Vin_high > 0.7*VCC per datasheet recommended operating conditions). Unless the module containing the AD9833 includes an additional clock buffer (such as low-voltage analog input to 3.3V digital output) between the AD9833 VOUT and the module's VOUT pin, something must change in how the oscillators are connected to the PWM drivers, such as adding an appropriate buffer to the oscillator output. Also, see further comments below in #9 on possibly eliminating this oscillator.

For more VOUT details, look at the AD9833 datasheet page 3 specs for VOUT maximum voltage, the diagram at the bottom of page 3, and the section "DIGITAL-TO-ANALOG CONVERTER (DAC)" on page 12. https://www.analog.com/media/en/technical-documentation/data-sheets/AD9833.pdf

Sorry, I didn't have time to try to search for a schematic for AD9833 module to understand if that module already includes some feature to create 3.3V digital output that would be compatible with GSCLK input. I'd strongly suggest look at the module output specifications to check the module's output signal level.

  1. The serial communications design is mixing a two different bus technologies that are not intended to work together. The TLC59482 driver contains a serial shift register, designed to daisy chain multiple drivers together, and using a variable length LAT pulse. The RF module connecting to J1 appears to be traditional SPI bus (don't have datasheet, so can't verify details, unsure why both CE and CSN needed...perhaps multiple SPI peripherals are on that module). The AD9833 appears to use a write-only SPI-like bus (3-wire). This peripheral combination seems like it will require complicated change of operation for the SCLK, SIN(MOSI), SOUT(MISO) pins when switching between LED on/off/PWM control and communications with the RF module or setting the oscillator. If RF communication bus needs to be active while LEDs are also being changed, this will potentially cause a big delay to periodic LED updates and very complex programming. Also, TLC59482 module pin 22 SOUT is constantly driven, even when LAT control is not active, to allow bits to shift through to next module. As drawn, there is electrical driver conflict between output from RF module connector J1 SOUT and the U3 SOUT pin 22, that may cause the RF module output signal to the microprocessor to be corrupted or unreliable. U3's SOUT is last in daisy chain, so will not be used, and its connection back to Teensy pin 14 CAN BE DELETED to avoid this conflict. The final SOUT output in U1-U2-U3 daisy chain is not needed to be connected unless you wanted the microprocessor to read back the delayed bits already sent for initial testing, but no useful functionality provided, so could place a test point on U3 SOUT or a not installed (open circuit) zero Ohm jumper (placeholder). I also strongly recommend allocating separate SOUT/SCLK + LATx pins from the Teensy for controlling the TLC59482 PWM outputs, that exclusively operate in serial shift mode, and not sharing those pins with other types of peripherals. Then assign a different Teensy SPI port configured for SPI mode that is shared between the RF module and the AD9833 input (if kept in design), keeping independent pins for CE/CN and FSYNCn to allow SPI bus sharing.

  2. I'm probably missing something special required for this POV virtual display technology application, which is not familiar to me .... but I don't understand why three independent precision GSCLK sources (the three AD9833 modules) are used to change PWM frequency of each LED bank. Varying the GSCLK input only controls the frequency of the LED PWM flicker when an LED is constantly on but not at full brightness. Turning the LEDs on/off and varying brightness can accomplished by software simply changing the GS register values via the SIN/SCLK/LATx serial shift input bus. If possible (but maybe not compatible with this application), I would eliminate all the precision oscillators and change the design to have all the TLC58484 GSCLK supplied by either: (1) one general purpose clock output from the Teensy to drive all three PWM driver GSCLK inputs with a fixed PWM frequency ,OR (2) use a cheap RC oscillator with digital output at fixed frequency (set by external R and C component values) to drive all three GSCLK inputs. If the precision oscillator is critical to control the flicker timing, then ignore this comment.

  3. Suggest you double-check the 3.3V power supply current budget (sum of all the 3.3V maximum currents required for each load). Based on schematic note that Teensy 3.3V output is maximum 250 mA, the RF module might need a larger current supply.

  4. For any Teensy clock outputs, I recommend adding a 33 ohm series resistor near Teensy connector pin (source end) before routing out to loads, so that source impedance tuning can reduce edge rise/fall to avoid transmission line effects, especially important for the multi-destination clocks. Also, check if the Teensy GPIO(s) used as clock output(s) have a "slow slew rate" configuration output (not sure if available in Teensy GPIO settings, but common on many programmable i/o pins). Slow slew setting will improves signal integrity for branched routing on slow clock distribution by avoiding very fast signal edges that can reflect from the load pins. As Tony also mentioned, the clock frequency doesn't determine signal integrity/crosstalk behavior (transmission line and reflection behavior), but rather the rising/falling edge timings are the critical factor that often cause problems with fast CMOS output drivers. I think the clocks in this design should all be running at less than 2 MHz, which is not high enough frequency to require fast edges.

Good luck.

  • \$\begingroup\$ First, thank you so much for all the time you took to write such a thorough answer. I can't say how nice it is to get feedback like this, seriously thank you. For my application, I actually need 3 independent and precisely controlled PWM frequencies (weird I know!), so I am interested in finding an appropriate buffer for the AD9833 output. Would the part I'm looking for be a level shifter, a clock buffer or something else? \$\endgroup\$
    – wootie11
    Commented Jul 6, 2021 at 14:45
  • \$\begingroup\$ @wootie11 Power plane layout looks good. Unfortunately, don't have time to review the trace layout, but given what I see so far and the ample space....I don't think you'll run into any problems. For the new LM321 op-amps, the feedback path needs to always be to the inverting input of the op-amp for stability. So swap the pin 1 and pin 3 connections, so that AOUT input signals go to pin 1 (in_P), and the resistor feedback network is on pin 3 (in_M). See the reference circuits in the TI LM321 op amp data sheet, fig 7. ti.com/lit/ds/symlink/lm321.pdf \$\endgroup\$
    – BK303
    Commented Jul 8, 2021 at 5:12
  • \$\begingroup\$ @wootie11 Also, when using the linear op-amp to scale the clock, make sure to program the clock oscillator for square wave output, not sine wave. The PWM drivers are expecting a sharp edged digital clock. I believe the non-inverting op amp with small gain should work in this application. There are probably some clock buffers that could do similar, but likely to have larger fanout (1 input to N outputs). \$\endgroup\$
    – BK303
    Commented Jul 8, 2021 at 5:41
  • \$\begingroup\$ Thanks for the feedback! I was wondering why my breadboard prototype wasn't working and after I flipped the inputs it worked like a charm! Also, I found that the AD9833 does actually provide VIN-level output for the Clock generator mode (MSB mode in the datasheet). It isn't referenced anywhere (strangely) but hooking it up to an oscilloscope shows nice 0-3.3V squares, so the op-amp won't be needed :'D Thanks so much for looking over my design again though and for the feedback! I now know how to wire the LM321 up correctly for next time at least B) \$\endgroup\$
    – wootie11
    Commented Jul 8, 2021 at 17:44


It's not the frequency that always counts but rise time for crosstalk and interference for capacitance. The -3 dB BW = 0.35 / Tr (10~90%)

Old CMOS was pretty forgiving as it was a fairly slow rise time. Now it's 100x faster with 3.3V logic.

If it's line frequency it shows up easier when R> 100k unless on a long wire.

For mutual coupling from inductance it depends on the co-parallel length of cable and current.

You will probably have common-mode SMPS noise issues that need to be filtered that get into unbalanced signal vs return path. So again decouple and twisted pairs or use a CM choke as a CLC Pi-filter on power or RF cap to earth.

Then to get a feeling for parasitic L and C touch a 10:1 10 Meg probe and measure E-field voltage then see how it attenuates with your hand over insulating paper or plastic to the scope ground. Fingertips are about 1pF in a few mm gaps and 100pF if touching lightly while the area of the hand is proportionally larger. So if it's noisy and long, use twisted pairs when possible. IF it's ringing add 150 Ohms in series with driver.

  • \$\begingroup\$ Thanks for the detailed response! I have a few questions - is there a good place you could recommend where I can brush up on some of the terms you use? I'm not familiar with CM choke, CLC Pi-filter, RF cap and some others. The idea of using your hand to test the parasitics sounds really nifty. Also, when you talk about twisted pairs, would it be possible to split a signal line and then 'twist' it on a PCB? I'm not sure I have signals that I can 'twist' really, but maybe I'm just misunderstanding your answer. Thanks for the help! \$\endgroup\$
    – wootie11
    Commented Jul 5, 2021 at 18:43
  • \$\begingroup\$ The archived book by Henry Ott is my suggestion. Clocks with a ground plane and/or adjacent gnd tracks offer some immunity. You might need a small dead time between muxing segments to prevent adjacent LED capacitance ghosting the next. \$\endgroup\$ Commented Jul 5, 2021 at 18:52

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