# How can I noise decouple an FPGA with multiple VCC/VCCIO/VCCA pins?

Currently I am working on a small project using a Max10 FPGA from Intel.

I know about decoupling IC using a capacitor in parallel and a ferrite in series. This works for a small amount of VCC pins. But the FPGA IC has multiple VCC, VCCA and VCCIO pins. Which of the following ciruit ways would be the best to go with?

• Use one ferrite for all pins and connect a capacitor after the ferrite to each pin.
• Use three ferrites. One for VCC, one for VCCA and one for VCCIO. Connect a capacitor after the ferrite to each pin.
• Use bypass capacitors only connected between VCC near the pin and GND.

Currently I would use the second solution, but I am not really sure.

• What does the appnotes say? what does the reference design show? TYPICALLY what I would do is 0402 (or 0201) of 1nF-10nF right at the via of a rail Ball. 100nF near the edge of the FPGA, 1uF + closer to the switcher to act as bulk. A ferrite to provide specific choking per-rail, with suitable damping
– user16222
Jul 6, 2021 at 10:27
• Okay, so TYPICALLY you would use one ferrite for VCC, one for VCCA and one for VCCIO? Jul 6, 2021 at 10:29
• maybe ... I typically use an Igloo2 and I have one for the 3v3 (VCCIO and VPP) and one for the 1v2 (VDD) so it really comes down to what do you want to protect?
– user16222
Jul 6, 2021 at 12:19
• Suggestions on passive components are not really precise. Each of the supplies will have a specific Power Supply Impedance vs Frequency demand, which you have to provide. While one of the rails could be happy with $0.1 \Omega$ impedance, another might need $5 m\Omega$. Once you know that, go simulate what you need (type and count of which caps, size and number of power planes). The manufacturers of the FPGA also offer tools for this, to include approximate parasitics, but Spice is probably more precise. Jul 6, 2021 at 12:32