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What I mean is that most abundant computing processors in market have the clock frequencies in the range of 2-4 GHz and from wikipedia:

As of 2012, the CPU-Z record for the highest CPU clock rate is 8.79433 GHz on an AMD FX-8350 Piledriver-based chip. As of mid-2013, the highest clock rate on a production processor is the IBM zEC12, clocked at 5.5 GHz, which was released in August 2012.

So, how do processors deal with the frequencies in the range of 20-100 GHz? Even if we consider a demodulation of data to lower frequencies from carrier frequencies, there needs to be a computing piece for doing that.

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    \$\begingroup\$ there needs to be a computing piece for doing that. Yes and that's why the baseband signal is downconverted so that it becomes, for example, a signal of 40 MHz which can easily be handled by a demodulator running at less than 1 GHz. My suggestion to you would be to study wireless communications a bit more to get a better understanding, as the question contains many assumptions that are simply untrue. [Edited by a moderator] \$\endgroup\$ Jul 7 at 7:18
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    \$\begingroup\$ They don't need to because there are dealt by Analog circuitry. \$\endgroup\$
    – Mitu Raj
    Jul 7 at 8:59
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    \$\begingroup\$ For an extreme example, think about (or look into) telecom lasers. The frequency gap is absurdly large there (10^14 Hz), but it's easy to inject rf modulation into the current supply for a laser diode with no computers involved. \$\endgroup\$
    – llama
    Jul 7 at 15:29
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    \$\begingroup\$ This question is remarkably bad. RF and Analog electronics have always run faster than digital electronics. And there are literally College Degrees worth of information to bridge the gap in understanding. This is the same question as "It's 1999. How do computers, which currently run at 80 MHz, handle VHF FRS Voice comms which are transmitted at 405MHz?" \$\endgroup\$
    – Jotorious
    Jul 7 at 17:37
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    \$\begingroup\$ The premise of the question neglects the underlying mechanisms and circuit design of analog and digital operation. A 100 GHz small-signal stimulus passing through a chain of analog elements is extremely dissimilar to trying to fully transition and saturate multiple stages of a register-to-register path in a CPU with a 1 / 100 GHz clock period, with large-signal considerations and tons of harmonics on top of most digital signals. \$\endgroup\$
    – nanofarad
    Jul 7 at 18:11
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So, how do processors deal with the frequencies in the range of 20-100 GHz?

They don't.

Even if we consider a demodulation of data to lower frequencies from carrier frequencies, there needs to be a computing piece for doing that.

No, there doesn't. There needs to be an analog piece for doing that.

Note that our goal is to design a circuit which takes the radio wave as an input, and produces the bits that the sender was trying to send as an output, and the bits are a much slower signal than the radio wave.

One typical way to do that, nowadays, is to first use analog filters to cancel out frequencies which are not the ones you are trying to receive, then use an analog mixer to shift the frequency down to a lower frequency, then feed that into an analog-to-digital converter. Now you still have a processing problem, but it's a slower processing problem. If your signal takes up 50.000-50.100GHz, you can shift it down to 0-0.1GHz = 0-100MHz (or maybe you might prefer 10-110MHz for various reasons). Now you just have a 100MHz or 110MHz signal to deal with.

You still have to process it though. So how might you do that? One way is to use a specialized computer chip - a Digital Signal Processor, or DSP - which is designed for exactly the kind of processing needed to receive radio signals. If you can run it at 500MHz, you still have only 5 instructions per cycle of your signal, but if you cut enough corners, it might be enough. You might be surprised how many corners you can cut. You will have the ability to run instructions in parallel, so perhaps you can process a group of 4 cycles together, in 20 instructions. A DSP is designed to get maximum number crunching for your buck, running the same code over and over. No branch predictors or caches here, just raw throughput.

Maybe you can't get a DSP fast enough. What other options do you have? One option is to split the signal in half. Instead of sending a 100MHz wide signal, split the data up, send 4 25MHz wide signals and then join the data together again after it's received.

Or, you can try an even faster processing device. An FPGA you string together as many separate processing stages as you can physically fit. If you need to add numbers at 200MHz... you can do that. If you need to add 50 numbers... you can still do it at 200MHz, but it will take up 50 times as much space because you actually set up 50 separate addition circuits on the chip, unlike a traditional processor, which only has a small number of addition circuits and has to reuse them 50 times in a loop.

If you are a big company that wants to produce 100000 of the same product, you might want to actually make a custom chip. It's pretty similar to an FPGA in principle, except you can't reprogram it, performance is better in every aspect, and it costs about ten million dollars to design so you'd better get it right the first time.


By the way, if you're wondering, in the old days, obviously there were no DSPs processing our signals - just analog circuits all the way through. But it turns out analog circuits are worse than DSPs, if your frequency is low enough to use one. They're more expensive, they're bigger, some of them use more power, and even worse, the laws of physics stop them from being shrunk down to mobile phone size. Yeah, today's phones would be impossible with that technology.

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  • \$\begingroup\$ Is there any relation between that stepped down frequency (0-0.1GHz) and the peak data rate that can be offered at that frequency? The 5G aims at peak data transfer speeds of > 10 GBPS and there are devices which support that. How much of a computational task is IOPS and is it strongly correlated with CPU clock? (and it seems that the memory I/O speeds have scaled up unlike processors with slowing of Moore's prediction)? \$\endgroup\$
    – lousycoder
    Jul 8 at 14:59
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    \$\begingroup\$ @lousycoder Rather than the stepped down frequency, you care more about the bandwidth (and the signal-to-noise ratio) via the Shannon-Hartley Theorem. A bandlimited signal that spans 99 MHz - 101 MHz is going to carry the same amount of into as a signal spanning 9 MHz - 11 MHz, or a baseband I/Q signal spanning "-1 MHz" to 1 MHz, assuming SNR is the same. \$\endgroup\$
    – nanofarad
    Jul 8 at 15:34
  • \$\begingroup\$ @lousycoder the answer you're looking for there is basically a whole signal processing textbook, but yes, the more bandwidth you have the higher data rate you can achieve. For a simplified picture: you modulate the carrier to make sidebands, each sideband has a certain width, and the data signal for each sideband is if the sideband is on or off. If you have more bandwidth you can fit more sidebands in, ie more parallel data channels. \$\endgroup\$
    – llama
    Jul 8 at 15:34
  • \$\begingroup\$ And the higher the frequency of the carrier, the more you can modulate it (so there's more available bandwidth). You can't modulate a 10 MHz signal at more than 10 MHz, but you can modulate a 10^14 Hz telecom laser by many many GHz \$\endgroup\$
    – llama
    Jul 8 at 15:39
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    \$\begingroup\$ @lousycoder perhaps engineering if you have a question about a machine, or chemistry if you have a question about a chemical, or electronics, if you have a question about an electronic part in a machine, or stack overflow, if you have a question about a piece of code in a machine, or crafts, if you have a question about making a paper mache dinosaur..... \$\endgroup\$
    – user253751
    Jul 19 at 14:32
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Certainly current general-purpose processors run in the low GHz clock speeds. However, purpose-designed circuits are capable of running at higher speeds. The parts of the circuit that need to handle the carrier and encode/decode data are quite limited and typically exchange data via buffers, so the CPU itself can handle data at much lower speeds. Similarly, relatively slow microcontrollers that feature USB2.0 interfaces have a small amount of high-speed circuitry while the processor core clocks in the low MHz. There are a few reasons why the whole CPU can’t run at multi-GHz such as power dissipation, production yield, and the need to be able to interface to other ICs without resorting to fancy PCB design tricks.

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The comparison is apples-to-oranges since a digital circuit is dissimilar to an analog one as far as its requirements and limiting factors for speed.

A limiting factor for digital speed is the propagation delay from storage element to storage element on the critical path - as a conceptual example, the output of a flipflop or similar, through a number of gates, to the input of another flipflop must be fast enough to reach the destination in time for the setup time requirement. In this case, you need to transition a number of stages, not at the clock speed of e.g. 100 GHz, but at a much faster edge, taking multiple steps.

On the other hand, for analog processing, you need to ensure that your 100 GHz +/- modulation bandwidth signal isn't rolled off too far at any given stage by parasitics and transistor speed. The transit frequency of MOSFET technologies has already reached the hundreds of GHz well before today's FinFET processes (e.g. a 65 nm CMOS process can pull off ft around 200 GHz according to some brief googling, but I am under NDA as far as anything else I can say regarding that or other processes), so with careful management of parasitics, even that old technology could pull off 10-20 GHz RF operation under a pessimistic assumption that we were limited by a tenth of the transit frequency at some stage. You can imagine the speed gain from there to today's single-digit-nanometer tech. I'm going to specifically ignore things like HEMT and BiCMOS processes here because I don't have confident numbers for them, but they'd only serve to strengthen the point of high analog speeds being achievable.

Of course, as soon as you get your 100 GHz RF signal through some passive analog filtering, your LNA, and your mixer, it's now at either around baseband or around some intermediate frequency that's much slower than 100 GHz. Filtering, digitizing, and processing it is now much simpler and you're free to use analog and/or digital techniques.

Follow-up to comment:

Is this unit stand alone or is there some real time fine tuning/feedback loop required between analog parts and the digital processor.

Often, the analog chains are either stand-alone or have slow feedback/control from the digital portion of the circuit. I don't know the state-of-the-art, but for the kind of RF chains I work on, there might be digital control of the tx/rx switch, perhaps switchable LNA gain/resonant elements for band selection, and control of the dividers in the PLL for the local oscillator, but not much more. That switching doesn't happen at high speed, and for the most part, the crucial high-speed bits are best implemented without the extra capacitance and load of complex digital circuitry tacked onto them to achieve that feedback.

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    \$\begingroup\$ Really appreciate the answer and the latest follow up remarks. \$\endgroup\$
    – lousycoder
    Jul 8 at 16:19
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A bit of simpler and more concise answer. 5G and other high frequency devices are implying the analog signal frequency they receive. However the way CPU/MCU communicate with those devices is digital. The data rate (not the wave frequency) carried over 5G is much lower and is something that those CPU and MCU can likely process. Then there is designated controller that receives analog signal and translates it to digital data (and in case of 5G vice versa) it then communicates that data to the CPU/MCU at the digital data rate that device can handle.

So in short: radio or other analogue frequency is not the same as effective data rate and does not translate to CPU clock speeds in any measurable way. You can use high frequency radio to transmit data at very slow data rates.

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