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I'm reading about Semiconductor Physics (Semiconductor - Physics and Technology), and I'm confused on one part of MOSFETs.

I understand the PN junction (FINALLY!) and all the basic level stuff. But I'm not sure I understand how a channel is formed between the two n+ regions. This image is pulled directly from the book.

I have drawn what I would consider to be "depletion" regions at thermal equilibrium (I'm guessing they'd look something like that).

With a positive voltage (forward bias) this region would shrink obviously....but the two n+ are still not connected. What exactly forms a channel between them?

edit: Also Side question.....in a MOSFET such as the one below....does where you connect the circuit (source or drain) actually matter. IE Could you put the drain on ground or source on ground and vice versa and it'd still work the same? (Since from the picture I don't see any differences?)

enter image description here

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To answer your last question first. THe source is defined by what terminal you connect your bulk connection. So no, there is no difference in the S/D until that connection is made. However, different process technologies impose different connections. In a typical CMOS (now-a -days) the substrate is using <100> P-type. Which means that the bulk is always connected to ground for NMOS (NMOS transistors are built in P-type wells). The PMOS, (built in N-Wells) can have a "floating" bulk connection because the N-Well to P-substrate will be reverse biased. For a PWell in P-sub connection (NMOS) you can see there is a direct connection.

MOS transistor gates are capacitors, when there is a voltage imposed on the gate (lets only talk about NMOS here, PMOS is the inverse) say a +'ve voltage. Electrons are attracted to the other "side" of the capacitor plate (this happens to be the channel) to balance the charge. the channel has p-dopants in it which when the voltage is applied get ionized by the E-field. This is what establishes the channel. The positive potential at the surface drives the holes away from the surface, leaving it depleted. The charge that is in the channel that equates the gate charge is due to the uncovered acceptor atoms (p-dopants).

As the gate voltage increases, the substrate can be seen to move through three separate regimes. The first (at low E-Field levels) the substrate is enhanced there are lots of majority carriers (holes). As the voltage increases the substrate goes into depletion and finally as the voltage increases further the substrate inverts and the channel connects to the electron reservoirs at the S/D ends. These regimes also correspond to the regimes of operation (roughly) as sub-threshold, triode and active regimes of operation.

This also explains the capacitance change of the gate wrt Vgb or Vgs (for S=D). Below the threshold, the charge on the gate sees the acceptor atoms which are distributed in depth, so the opposite electrode to the capacitor looks almost "fuzzy" to it. i.e. the effective E-field can be thought to penetrate a little further, which decreases capacitance. Once the channel is established, all those electrons are gathered up close to the surface, the distance between plates is decreased and the capacitance is increased.

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  • \$\begingroup\$ So to put it simply, + charge applied on the top attracts electrons to the lower side of the plate (in between the 2 N regions on the Source and Drain) and as the voltage increases the electric field pushes away any holes from the Electron "channel" that has been created? And the holes near the plate get filled in by these electrons forming a - ionized atom. and a negative electric field pushes the electrons away so thats what the "max" saturated operation would be? or am I backwards? \$\endgroup\$ – user3073 Feb 10 '13 at 5:41

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