0
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This is my original file saved as "example.v"

module example(a,b,y);
  input b,y;
  output a;
  assign a=b&y;
endmodule

This is my testbench file saved as "example_tb.v"

module testbench; 
    reg t_x, t_y; 
    wire t_z; 
    example DUT ( t_z, t_x, t_y ); 
    initial 
        begin 
            $dumpfile(“example.vcd”); 
            $dumpvars(0, testbench);
            $monitor ($time, "t_x=%b, t_y=%b, t_z=%b",t_x, t_y, t_z); 
            #5  t_x = 1’b0; t_y= 1’b0; 
            #5  t_x = 1’b0; t_y= 1’b1; 
            #5  t_x = 1’b1; t_y= 1’b0;
            #5  t_x = 1’b1; t_y= 1’b1; 
            #5  $finish;
        end 
endmodule

Command I runned:

iverilog -o mysim example.v example_tb.v

Error reported:

example_tb.v:7: syntax error
I give up.
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4
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Your apostrophe chars are the problem

 $dumpfile(“example.vcd”);

should be

 $dumpfile("example.vcd");

And for all the literals, such as,

#5  t_x = 1’b0; t_y= 1’b0;

they should be

#5  t_x = 1'b0; t_y= 1'b0;
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2
  • \$\begingroup\$ Perfect, Thank you! \$\endgroup\$ Jul 9 at 6:26
  • \$\begingroup\$ Typical copy-paste bug! \$\endgroup\$
    – Mitu Raj
    Jul 9 at 7:12

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