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I am experiencing a very unusual problem (at least for me). When I touch with my fingers, or the oscilloscope probes, on the crystal or it's capacitors, the PIC runs slower...and A LOT slower then it should...with my fingers, most of the time it comes back to the real speed, but with the probes, it hangs forever.

I am running the PIC18F2550 at 48MHz with a 20MHz crystal...I supose I am maybe changing the capacitance "seen" by the PIC across the crystal and the oscillation circuit is going nuts..does it makes any sense? And if it does, what may I do to correct it?

EDIT:

The pictures below shows the circuit. The blue picture is the Bottom Layer of a 2 layer FR4 170Tg/290T ENIG board. I have highlighted the oscillator's traces, it's possible to see the ground plane, connected to both capacitors and the crystal in the middle, between them. The red picture is the Top Layer, where there is a big (and highlighted) ground plane, and some traces for two LEDs. There is also a transparent mix of the Top and Bottom layer, so see how they interact with each other. It's possible to see the PIC's orientation and schematics of this part of the project by the oscillator traces.

The problem only appears when the OSC1 capacitor is completly touched, or the OSC1 pin at the PIC is touched. Touching the traces or OSC2 capacitor doesn't bring any harm, as expected.

The Crystal:http://www.digikey.com/product-detail/en/NX5032GA-20.000000MHZ-LN-CD-1/644-1039-1-ND/1128911

The Crystal's Capacitors:http://www.digikey.com/product-detail/en/12061A150JAT2A/478-1439-1-ND/564471?cur=USD

EDIT2: The finger can have a 5pF to 15pF capacitance, so probably there is no much that can be done...http://ww1.microchip.com/downloads/en/AppNotes/01101a.pdf (page 2) Removing the ground plane as pointed out in the answers is worst.

Bottom Layer

Top Layer

Bottom and Top Layer

The Oscilloscope waveforms:

OSC1 before being touched:

OSC1 before being touched

OSC1 after being touched:

OSC1 after being touched

OSC2 before OSC1 being touched:

OSC2 before OSC1 being touched

OSC2 after OSC1 being touched:

OSC2 after OSC1 being touched

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    \$\begingroup\$ 20MHz to 48Mhz you ask? See the datasheet page 24. It has a 96MHz PLL with an input of 4MHz, so divide 20MHz by 5 using prescaler, and input to the 96MHZ PLL, which has a divide by 2 on the other side for 48MHz. \$\endgroup\$ – Oli Glaser Feb 8 '13 at 21:12
  • \$\begingroup\$ I am using HSPLL, since I have USB communications \$\endgroup\$ – mFeinstein Feb 8 '13 at 21:18
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    \$\begingroup\$ When you probe the crystal, probe on the OSC2 pin as this is the low impedance side. Use the 10x setting. Probing the OSC1 side may throw it out even if the circuit is okay. \$\endgroup\$ – Oli Glaser Feb 8 '13 at 21:19
  • \$\begingroup\$ Also : is the case of the crystal connected to 0V? It should be. \$\endgroup\$ – Brian Drummond Feb 8 '13 at 21:34
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    \$\begingroup\$ @OliGlaser the 10x probing worked well...I have a ground plane beneath the crystal, so I think this is the problem, since my finger and the ground plane will be another capacitor seen by the circuit...(I will provide the files shortly) \$\endgroup\$ – mFeinstein Feb 9 '13 at 22:39
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I had a look at things and although what you are seeing when you load the high impedance pin of the oscillator is to be expected, it is still possible your circuit is not optimal.

Ideally the crystal traces would be as short as possible, with no high frequency/current traces crossing those traces at any point (also running under the micro is not ideal). In short the crystal and it's load capacitors will be as close to the pins as is practical.
Also, a ground "shield" trace running around the outside of the oscillator traces, and a local ground plane underneath the crystal can help reduce any external noise issues. These would be connected directly to the microcontrollers Vss at one point (if a ground plane layer is present, the capacitors can be grounded through vias to this)

I don't know what the other traces crossing your crystal traces are carrying (so how much of an issue they would be), but be aware of issues here. Also the traces are longer than is ideal.

Here is an example layout:

Oscillator Layout

To test how marginal your circuit may be, you need to see if it starts and runs okay over your operating temperature range. So cool/heat the circuit as necessary and cycle power to see if the oscillator starts correctly. If you apply a slight change and it doesn't start, you need to fix it.
Similarly, you need to determine how susceptible it is to noise. This is difficult to do "scientifically", but placing a noisy circuit (e.g. something that switches quickly with high current) near the oscillator can give you an idea of how easily it can be affected. How much of a concern this is depends on whether your circuit is intended for e.g. automotive/industrial or less noisy environments.

If you discover the circuit is marginal, then it could be that the drive is too high or low, both of which can cause issues. For a high frequency like 20MHz, a higher drive level is needed, so with a PIC this would correspond to the HS setting. If the drive level is too high, a series resistance can be included to adjust the drive as necessary (or with the PIC XT mode could be tried). Loading capacitance needs to be calculated/adjusted to include stray capacitance (CL1 || CL2 + Cstray - see app notes below for details) Another possibility is the crystal itself is not ideal, so trying another crystal is also an option.

When testing, ideally a 100x or FET probe would be used, and AC coupling the scope input will reduce loading also. If a 10x probe is used (or even a FET probe ideally), then you need to account for the extra capacitance by lowering the load capacitor on that side.

There are various ways of testing your oscillator to make sure it's stable/reliable. As well as the temperature tests, testing adequate drive can be done e.g. adding pot in series with the crystal, and increasing until the oscillator fails. When you reach this point the potentiometers measured value should be at least 5 times the crystal ESR to provide adequate gain over all conditions. This, and other methods of testing are discussed in the first link of helpful App notes below:

Making Your Oscillator Work (pretty good note on various methods of testing)
ST Oscillator Design Guide (layout diagram above came from this note)
EFM Oscillator Design Considerations
Crystal Oscillator Troubleshooting Guide - Freescale (examines common problems)
Design an Oscillator to Match your Application - Maxim (lots of useful theory)
Oscillators For Microcontrollers - Intel (old, but still very relevant)


Experimental data and scope shots

To add some direct data obtained by myself to the above, I took a dsPIC prototype with a 4MHz crystal (sorry, no boards with a 20MHz crystal to hand - the principle is exactly the same in any case) which was made up on breadboard (so an "ideal" layout is not really possible) and probed both OSC pins with a standard 10x probe. The purposes were to find out whether I could stop the oscillator, and to take a couple of example scope shots to see how it was performing.

The result was probing either side did not stop the oscillator, but it looks like the crystal is slightly overdriven (espcially since extra loading should reduce the gain a little)
Touching the pins did not even cause it to stop, however pressing firmly on the lead (high impedance side) of the 1 MΩ resistor I had put across the oscillator created enough capacitance to cause the amplitude to drop and the clipping to stop (a rough indication a little more load capacitance or a series resistor reduce drive slightly would be a good idea)

The overdrive is not of a concern for a breadboard prototype, since the oscillator does it's job and is very solid. However, the overdrive could eventually cause premature failure so would be an issue when designing for production. Ideally you would want enough drive to make it difficult to disturb the oscillator, but not too much so as to overdrive the crystal (so a nice sine wave at both sides).
This is easier said than done, as it requires the correct tools/approach, so is why in many cases engineers just follow the recommendations and hope for the best. This is not the best approach, as what may work fine at 25°C may not work at 35°C. So although it may be difficult to do, testing the oscillators performance at design time may save a lot of trouble later on.

Anyway, enough preaching, here are the pictures:

Board (sorry for bad lighting) - notice although it's messy, the crystal and caps (blue) are very close to the pins. The 1MΩ resistor across OSC1 and OSC2 is closest to the edge.

Board picture

OSC 2 low impedance side (slightly overdriven):

dsPIC Low Impedance side

OSC1 pin high impedance side:

dsPIC high impedance side

High impedance side with finger pressed firmly onto OSC1 (using resistor lead mentioned) Notice reduced amplitude and sine wave shape:

dsPIC high impedance side finger

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I think that maybe that pair of capacitors usually in the 10's of pF are not well chosen. Check the crystal specs. I'd suggest 10, 15 or 22pF but it depends on the crystal and up to some extent to the layout and oscillator circuit. Microchip datasheets also have some advice on oscillator components. Whenever you touch a oscillator circuit with your finger or a probe, you are basically adding a capacitive load which usually dampens the oscillation and stops the clock but some times (it could be your case) make the crystal oscillate into a harmonic frequency. It's not so unusual.

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  • \$\begingroup\$ I am using 15pF \$\endgroup\$ – mFeinstein Feb 8 '13 at 21:18
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To first understand what is happening you need to understand HOW oscillators work and XCO's in particular. XCO = Crystal Controlled Oscillator. X is short hand for Crystal AKA XTal.

Fundamentally an oscillator is simply an amplifier that has 180 degrees phase shift at the frequency of interest. If you can support that, whilst suppressing other phases then your oscillator will run at the frequency at which the phase is 180 degrees and no other.

Typically, simple oscillator are logic inverters with the output driving through a delay element, or even a filter back to it's input. SO the output will be low impedance and the input will be high impedance. Crystals can be manufactured and easily tuned to given delays/filter characteristics very reproduce-ably so are a natural fit. The capacitors you use with them are used to filter out (in some cases) harmonic/tones that you want to suppress, since crystals are resonant devices, they can have overtones and harmonics.

In other cases it is desired to "pull" the XCO to a slightly different frequency by adversly affecting the delay through the crystal. You would do that by changing the C value of the input side of the amplifier used in the oscillator. This change in C, changes the delay, which represents a different value of phase for a given frequency.

Not all oscillators are as sensitive, but it is well known that certain types are. And indeed, some manufacturers have recommendations on how to lay out your PCB to prevent stray fileds, leakage and EMI/RFI from affecting your frequency and even jitter.

The TLDR version:

  1. don't touch the XTal or the Input to the oscillator. Your result is not surprising.
  2. if you must, as mentioned in the comments, probe the output side of the oscillator's amplifier as it will have much lower impedance and MIGHT be able to handle the increased loading.
  3. Or use a low C probe - like a FET probe on your 'scope
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    \$\begingroup\$ Some MCU's have clock output pins which you can use to probe the clock signal. \$\endgroup\$ – helloworld922 Feb 8 '13 at 22:28
  • \$\begingroup\$ exactly, that's a good point to raise for that case. There are many variants. \$\endgroup\$ – placeholder Feb 8 '13 at 22:43
  • \$\begingroup\$ @rawbrawb could you look at the pictures I added to the question, and give me some recommendations? Thank you! \$\endgroup\$ – mFeinstein Feb 10 '13 at 17:58
  • \$\begingroup\$ @mFeinstein the first ting I notice is that your XTal is far from the pins, the 2nd thing I notice is that trace capacitiance is different from one side of the Xtal to the other. Removing the ground plane does reduce the stray capacitance but increases the coupling capacitance to potential aggressors signals (as Kortuk pointed out). You've shown so far that they system is sensitive (your "finger" experiment) could you get a better placement? \$\endgroup\$ – placeholder Feb 11 '13 at 22:14
  • \$\begingroup\$ @rawbrawb I was thinking the same when I was designing the board, but since it worked well in the protoboard, I figured the traces differences and distance wouldnt be a problem, since in the breadboard things were a lot far away from the pins. The board is very small with lots of stuff, so I dont think I might place them any closer, not in the same layer, and placing in another layer will add the inductance of the vias. What do you think of leaving the ground plane in the bottom (blue layer) and only removing the ground plane from the top (red layer)? \$\endgroup\$ – mFeinstein Feb 12 '13 at 0:56

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