I realized 4 boards from the circuit in attached file based on the HV9961 a constant current led driver controller: http://ww1.microchip.com/downloads/en/devicedoc/20005588a.pdf. Each stage, powered by a 1:1 transformer delivering 340VDC rectified and filtered voltage, can drive a 175V leds string up to 700mA with a PWM on connector J9. Everything is ok but when the PWM returns to 0%, the current drops to 0amps into the 3 LEDs strings of the 4 boards (it's normal) but the voltage Vbulk increases up to 640V.

Please, can you explain me this phenomenon and how to fix this voltage increase ?


LEDS drivers multi channels

  • \$\begingroup\$ Just from the fact that your DC voltage about doubles I'd be suspecting that L1, L2, and L3 are the culprits. Since you don't have any current in the LEDs, there's probably no voltage across those nearby caps, so the inductors could get 340 V placed across them if the FETs are switched even for quite short moments and then flyback through those diodes back onto Vbulk. Can you scope their gates? Are they at all active? But no, I don't know and haven't spent much time looking. It's just that the measurements you gave seem to point a finger at L1, L2, and L3. \$\endgroup\$
    – jonk
    Commented Jul 11, 2021 at 3:45

1 Answer 1


I don’t see any problems with this no load voltage. The cap voltage stress is limited by the LED string Vf when off . The FETs are rated for 650 V which is the Vdc reduced by the LED off Vf.

The possible causes

Transformer ratings of 1:1 are at full rated load but depending on VA rating and loss factors with cap ripple voltage, it might be 1:1.2 (120%) or 1.1 110% with no load.

If @jonk is correct, it would mean your off state is not quite off and the inductors are acting as a buck-boost circuit with narrow pulses and no load in boost mode. The way to diagnose this is to ….

  1. Verify V at LD is lower than threshold.
    • “ LD = This pin is the linear dimming input, and it sets the current sense threshold as long as the voltage at this pin is less than 1.5V. If volt- age at LD falls below 150 mV, the gate output is disabled. The gate signal recovers at 200 mV at LD”
  2. Remove the circuit from the bridge caps and measure no load voltage. It should be less than 120% * 1.414 (rms to pk) * 240 V = 407 Vdc.
  3. Then measure bulk Cap: Vavg AC ripple and Vdc on the Vdc supply from 0 to full load where droop is:
    • Ic=700 mA = CdV/dt for C=300uF and dt = 10ms,
    • dV= 700 mA * 10ms / 300 uF = 23 V or ~ 6% ripple so OK


  • Verify isolation transformer DC separate from cct. Consider a dummy preload 10%.
  • Verify LD pin is below threshold, add shunt R if necessary to turn off gate.

Considering the high voltages, there is not much safety added using a 1:1 isolation transformer if performance adds VI heat loss to FET at certain power levels. Consider removing and using a better supply. ( e.g. OEM CC supply)

  • Report any other anomalies and results in Question pls.
  • \$\begingroup\$ Thanks for the additions. +1 \$\endgroup\$
    – jonk
    Commented Jul 11, 2021 at 7:44
  • \$\begingroup\$ Thanks, I will check all these points. But if L1 L2 L3 keep get a charge after PWM off, I think they have to discharge into the LEDs through the Schottky diode. So, LD point voltage of the HV9961 is not a problem at switch off. \$\endgroup\$
    – Teddol
    Commented Jul 11, 2021 at 11:34
  • \$\begingroup\$ If LD < 150mV then no boost since no gate pulses otherwise that is your problem \$\endgroup\$ Commented Jul 11, 2021 at 13:06

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