2
\$\begingroup\$

I'd like to start generating (and perhaps also capturing) composite video (PAL) signals from a digital source, eg. FPGA. However, while my digital logic/programming skills are covered, I'm lacking a lot of fundamental analog concepts, and I'm a little lost.

From what I understand, the idea basically boils down to outputting the correct voltage at the correct times from an output pad on my FPGA. I'm thinking that the entire signal (including sync pulses/color carrier modulation/etc) could be generated in the digital domain, and then passed through a DAC. I don't think I'll have much issue figuring these parts out.

The output voltage from the DAC needs to be connected to an output terminal. Already here I'm wondering how this would work - what do I need to worry about? I assume it's not enough to just connect the DAC output pin and ground to the terminal? What kind of current would I need the pin to output/source? What kind of current needs to be on the terminal? Might I need some kind of amplifier/protection circuit in between them? Are these even relevant questions?

From the terminal, the signal would then be transmitted along a composite RCA cable to the receiver on the other end. I know that composite video cables have a characteristic impedance of 75ohms, but I'm not sure what that means beyond knowing I have to match it with my output, which I also don't know how to do. Is this related to my previous questions?

Is there anything else obvious that I'm already overlooking?

I'm also curious about how this might work for audio signals, though I guess it's all the same in theory, just with perhaps some different parameters and maybe some filtering (eg. DC blocking) for the "pure" AC stuff?

Any and all guidance/responses appreciated. Thanks in advance!

\$\endgroup\$
4
  • \$\begingroup\$ Easiest way is to set a sample rate of 4*Fsc (or some higher multiple, but 4x is adequate); some BBC broadcast gear in the 1980s did that. If you can't find a 4*fsc crystal, use a DCM or PLL in the FPGA to generate a suitable clock from an Fsc oscillator (4.43361875Hz IIRC) \$\endgroup\$
    – user16324
    Commented Jul 11, 2021 at 19:28
  • \$\begingroup\$ Did you stumble across reconstruction filtering? That's something you always need after a DAC! \$\endgroup\$ Commented Jul 11, 2021 at 19:56
  • \$\begingroup\$ I was not aware of reconstruction filtering, thanks for the tip! The wikipedia article has made this very clear. \$\endgroup\$
    – ferris
    Commented Jul 11, 2021 at 20:32
  • \$\begingroup\$ Try posting FPGA QUESTION HERE \$\endgroup\$
    – Bill Moore
    Commented Jul 12, 2021 at 13:55

2 Answers 2

1
\$\begingroup\$

The composite signal will have a swing as much as 1V or so, including sync, driving into 75 ohms. Plan for 1.1V. This can be driven by a DAC directly assuming it has a suitable swing (for example, a ‘video DAC’). A DAC of at least 10 bits, followed by a buffer with a low-pass reconstruction filter is recommended.

The video output signal can be referenced to the sync tip as minimum DAC voltage. The video blank level will be 300mV above that, with peak signal 700mV above that for PAL. NTSC is slightly different due to its use of setup but will be similar.

This app note gives further details: https://www.analog.com/en/technical-articles/video-signal-distribution-using-low-supply-voltage-amplifiers.html#

As to how to synthesize the signal, your source is likely to be 13.5 MHz 4:2:2 signals (27MHz base clock.) Your subcarrier will be different, but it’s possible to synthesize a version in 27MHz domain using a digital synthesizer. You then create the U/V pair (should be low-pass filtered), modulate each with its subcarrier phase (V phase shifted 90 degrees from Y), add to Y, then finally add to sync and blank level to create the composite signal.

There’s also some fine details about interlace and special handling of subcarrier phase to consider, as well as wave shaping sync. Finally, using up sampling before the DAC will improve performance.

If you’re doing this for a learning experience I suggest getting a copy of the Keith Jack ‘Video Demystified’ book as a starting point. If you’re doing it as a project that has a budget and schedule, consider using a known-good IP block instead.

\$\endgroup\$
5
  • \$\begingroup\$ I'm indeed looking into this as a learning experience - that book looks like an excellent resource, thanks for the tip! \$\endgroup\$
    – ferris
    Commented Jul 11, 2021 at 20:21
  • \$\begingroup\$ I think I'll be able to handle the encoding details; I'm more concerned with the analog components, as I don't really know what I'm doing in that domain. For example, what does "swing" mean? And when you say "this can be driven by a DAC directly" how would you know that/how might I check/configure a DAC properly? I guess I can sum up what I'm asking as "how do I correctly convey my video signal voltage from the DAC all the way to the receiver" (and I realize I'm only at the tip of an iceberg, hit me!) \$\endgroup\$
    – ferris
    Commented Jul 11, 2021 at 20:25
  • \$\begingroup\$ You’re overthinking it. A typical ‘video’ DAC can drive composite or component signals. It just needs to be able to source enough current that it can produce the 1V-ish swing into 75 ohms, at the final sample rate you choose. As I noted, adding a buffer with a reconstruction filter will improve things. The ADI appnote shows examples of buffers. \$\endgroup\$ Commented Jul 11, 2021 at 20:50
  • \$\begingroup\$ I did it the hard way - designed one from scratch to go into a chip. Difficulty: also needed to support component and HD output with the same 3 DACs. Most of the effort was in the sync gen and filters. \$\endgroup\$ Commented Jul 11, 2021 at 21:16
  • \$\begingroup\$ Thanks for the help and links; indeed the app note gave me what I was looking for electronically. \$\endgroup\$
    – ferris
    Commented Jul 12, 2021 at 8:18
0
\$\begingroup\$

The composite video output needs to have 75 ohm output impedance, and the voltage levels needs to be 1Vpp when terminated into 75 ohms input device. The 1Vpp is from sync tip to white, with 300mV for sync and 700mV for white. Color modulation adds some amplitude, so e.g 100% yellow has 1.233Vpp.

Basically you need a DAC with sampling rate of 17.734475 MHz to generate PAL color composite signal digitally. There's even a standard for that.

What might be best is to simply get a video DAC chip if you want to drive that directly, or a PAL encoder chip which can generate all the hard work of PAL encoding and cable driving for you so you only need to feed it with digital YCbCr color data.

\$\endgroup\$
3
  • 1
    \$\begingroup\$ PAL encoder chips seem so complicated. I guess it depends on where OP wants the complexity to be. My head was spinning reading the datasheet I thought cooking up the signal might be more straightforward. \$\endgroup\$
    – DKNguyen
    Commented Jul 11, 2021 at 20:12
  • \$\begingroup\$ @DKNguyen Most just need few register writes over I2C and that's it. The encoder chips take in digital data and encode PAL and have analog output that is directly capable of driving composite out to a TV. It takes all the complexity away from PAL encoding algorithm, choosing a suitable DAC and buffering the DAC output. \$\endgroup\$
    – Justme
    Commented Jul 11, 2021 at 20:19
  • \$\begingroup\$ To clarify, I'm doing this as a learning exercise, and I'm particularly interested in the analog parts of the chain - in particular, "choosing a suitable DAC and buffering the DAC output" - I'd like to know how that works, eg. how I might build my "own" circuit(s) to achieve these parts, and what concern(s) I would have along the way. \$\endgroup\$
    – ferris
    Commented Jul 11, 2021 at 20:20

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.