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I am trying to use a divider in order to make a modulus 10 counter on a Basys3 FPGA. The frequency of the FPGA's clock is 100 Mhz.

I am getting the following warning when I try to use the clock divider to generate the clk signal that should be used in the modulus 10 counter

Gated clock check: Net ... is a gated clock net sourced by a combinatorial pin...

enter image description here Is there anyway I can get rid of this warning while I do what I described?

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

library xil_defaultlib;
use     xil_defaultlib.slotMachineUtilities.all;
entity divisor is
    generic(
        i_counting_limit_as_xth_of_second: unsigned(9 downto 0) := "0000000101");
    port (
        rst                 : in  STD_LOGIC;
        clk                 : in  STD_LOGIC; --Basys3 has a 100 Mhz clock
        o_counting_limit_reached: out STD_LOGIC
    );
end divisor;

architecture divisor_arch of divisor is

    SIGNAL counter, next_value: unsigned(33 downto 0);
    constant ONE_XTH_OF_SECOND_WITH_100MHZ_CLK: unsigned(33 downto 0) := NEW_CYCLES_PER_CYCLE_OF_DIVISOR(IS_IMPLEMENTATION);
    signal s_limit: unsigned(43 downto 0);--counting_limit_as_number_of_clk_periods
   
begin
    s_limit <= i_counting_limit_as_xth_of_second * ONE_XTH_OF_SECOND_WITH_100MHZ_CLK;  
    o_counting_limit_reached <= '1' WHEN (counter = s_limit) ELSE '0';

    p_next_state: process(counter, s_limit)
    begin
        IF (counter = s_limit) THEN 
            next_value<= (OTHERS=>'0');
        ELSE
            next_value <= counter + 1;
        END IF;
    
    end process p_next_state;
    
    p_register:
    PROCESS(clk)
    
    BEGIN
        
        IF(rising_edge(clk)) THEN
            IF (rst='1') THEN
                counter<= (OTHERS=>'0');
            ELSE
                counter<= next_value;
            END IF;
        END IF;
    END PROCESS p_register;

end divisor_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
USE IEEE.numeric_std.ALL;
library xil_defaultlib;
use     xil_defaultlib.slotMachineUtilities.all;
entity mod_x_counter is
port (
      rst: in std_logic;
      clk: in std_logic;
      clk_start_stop: in std_logic;
      i_start: in std_logic;      
      i_stop: in std_logic;
      o_counter : out integer range 0 to MODULUS_LIMIT-1);

end mod_x_counter;

architecture Behavioral of mod_x_counter is
SUBTYPE t_counter_state is integer range 0 to NUMBER_OF_STATES_OF_MOD_X_COUNTER-1;
SIGNAL s_state: t_counter_state:=0;




signal s_next_state: t_counter_state;

signal s_counter_enabled: std_logic:='0';
begin


--process that models combinational circuit to calculate the next state of the Moore Machine
p_next_state:process(s_state, s_counter_enabled)
begin

if ((s_state>=0) and (s_state<MODULUS_LIMIT-1) and (s_counter_enabled='1')) then
    s_next_state<=s_state+1;

elsif (s_state=MODULUS_LIMIT-1 and (s_counter_enabled='1')) then
    s_next_state<=0;

else
    s_next_state<=s_state;
end if;
o_counter<=s_state;
end process;

p_counter_state:process (clk)

begin
if (rising_edge(clk)) then
    if (rst='1') then
        s_state<=0;
    else
        s_state<=s_next_state;   
    end if;
end if;

end process;

--process modeling register and output
--process (clk_counting)

The mod_x_counter receives two clocks:

  • the Basys3 clock at the clk_start_stop input signal. This first clock gets used to know when the counting state must be changed between running and stopped.
  • o_counting_limit_reached generated by the divider at the clk input signal. This second clk gets used to known when the counter's value must be changed.

i_start and i_stop get calculated by debouncing two buttons of the FPGA. One of them gets used to set the counter in running mode and the other gets used to stop the counter.

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In the end I got rid of the mentioned warning by using the gated clock generated by the divider as an enable signal (i_enable) after checking for rising_edge(clk) where clk is the Basys 3 100 Mhz clock.

You can find the code as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
USE IEEE.numeric_std.ALL;
library xil_defaultlib;
use     xil_defaultlib.slotMachineUtilities.all;
entity mod_x_counter is

port (
      rst: in std_logic;      
      clk: in std_logic;
      i_enable: in std_logic;
      i_start: in std_logic;      
      i_stop: in std_logic;
      o_counter : out integer range 0 to MODULUS_LIMIT-1);

end mod_x_counter;

architecture Behavioral of mod_x_counter is
SUBTYPE t_counter_state is integer range 0 to NUMBER_OF_STATES_OF_MOD_X_COUNTER-1;
SIGNAL s_state: t_counter_state:=0;




signal s_next_state: t_counter_state;

signal s_counter_enabled: std_logic:='0';
signal s_next_counter_enabled:std_logic:='0';


begin


--process that models combinational circuit to calculate the next state of the Moore Machine
p_next_state:process(s_state, s_counter_enabled, i_enable)
begin

if ((s_state>=0) and (s_state<MODULUS_LIMIT-1) and (s_counter_enabled='1') and (i_enable='1')) then
    s_next_state<=s_state+1;

elsif (s_state=MODULUS_LIMIT-1 and (s_counter_enabled='1') and (i_enable='1')) then ---and (s_already_counted<='0')) then
    s_next_state<=0;
else
    s_next_state<=s_state;
end if;
o_counter<=s_state;
end process;



p_counter_state:process (clk)

begin

if (rising_edge(clk)) then
    if (rst='1') then
        s_state<=0;        
    else
        s_state<=s_next_state;                
    end if;
end if;

end process;


p_next_counter_enabled: process(s_counter_enabled,  i_stop, i_start)
begin

if (i_stop='1') then
        s_next_counter_enabled<='0';

elsif (i_start='1') then
        s_next_counter_enabled<='1';
else
    s_next_counter_enabled<=s_counter_enabled;        
end if;

end process p_next_counter_enabled;

--process modeling register and output
--process (clk_counting)

p_counter_enabler:process(clk)

begin

if (rising_edge(clk)) then
    if (rst='1') then
        s_counter_enabled<='0';
    else
        s_counter_enabled<=s_next_counter_enabled;
    end if;
end if;


end process p_counter_enabler;

end Behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

library xil_defaultlib;
use     xil_defaultlib.slotMachineUtilities.all;
entity divisor is
    generic(
        i_counting_limit_as_xth_of_second: unsigned(9 downto 0) := "0000000101");
    port (
        rst                 : in  STD_LOGIC;
        clk                 : in  STD_LOGIC; --Basys3 has a 100 Mhz clock
        o_counting_limit_reached: out STD_LOGIC
    );
end divisor;

architecture divisor_arch of divisor is

    SIGNAL counter, next_value: unsigned(33 downto 0);
    constant ONE_XTH_OF_SECOND_WITH_100MHZ_CLK: unsigned(33 downto 0) := NEW_CYCLES_PER_CYCLE_OF_DIVISOR(IS_IMPLEMENTATION);
    signal s_limit: unsigned(43 downto 0);--counting_limit_as_number_of_clk_periods
   
begin
    s_limit <= i_counting_limit_as_xth_of_second * ONE_XTH_OF_SECOND_WITH_100MHZ_CLK;  
    o_counting_limit_reached <= '1' WHEN (counter = s_limit) ELSE '0';

    p_next_state: process(counter, s_limit)
    begin
        IF (counter = s_limit) THEN 
            next_value<= (OTHERS=>'0');
        ELSE
            next_value <= counter + 1;
        END IF;
    
    end process p_next_state;
    
    p_register:
    PROCESS(clk)
    
    BEGIN
        
        IF(rising_edge(clk)) THEN
            IF (rst='1') THEN
                counter<= (OTHERS=>'0');
            ELSE
                counter<= next_value;
            END IF;
        END IF;
    END PROCESS p_register;

end divisor_arch;
```
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