1
\$\begingroup\$

Large multiplexers can take a lot of logic and limit fmax of a design e.g a mux that selects one of 8 512-bit words. I think an alternative to this is to use a shift register where the maximum latency to select a word will be equal to number of words being selected.

Assuming that latency is acceptable, a shift register can be used in place of a giant mux.

Now my question is, is such a thing ever done in practice? Will it really give logic saving since a shift register like this won't contain just registers but some logic will still be required to make it work. Is there a name for replacing a mux with shift register in this way?

\$\endgroup\$
2
  • 1
    \$\begingroup\$ Yes it's done. Sometimes it'll give a saving (especially in Xilinx FPGAs < 15 years old where the LUTs all have a hack for the job). Only way to know if the savings are worthwhile for your application is to try it. Xilinx call it SRL16 (but that's a proprietary term) xilinx.com/support/documentation/application_notes/xapp465.pdf \$\endgroup\$
    – user16324
    Jul 13, 2021 at 11:24
  • 1
    \$\begingroup\$ You can pipeline the mux fairly easily if the frequency is a problem, but you need high throughput. Another option on an FPGA if high throughput isn't necessary would be to use LUTRAMs and write all your inputs into a memory and then read the appropriate one. I think you'd get better latency that way than using it as a shift register. \$\endgroup\$ Jul 13, 2021 at 17:38

1 Answer 1

1
\$\begingroup\$

This sounds like a job for a dual-port circular buffer RAM. Then you leverage the optimized select logic in the RAM block instead of instancing an explicit mux.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.