LM324 are not paragons of accuracy, and I would not bother with difference amplifiers either, since those only add to the errors. Instead, I'd convert battery voltages to currents, and multiplex each current between two load resistors - one of them a dummy, another fed to a buffer feeding the ADC.
The battery (+) voltages up to about 13V relative to BATT_GND would work with the following circuit:
simulate this circuit – Schematic created using CircuitLab
V3 represents the measured cell, V2 are the cells below it, V4 are the cells above it.
Each battery channel has its own R4. R5 and OA3 is common to all channels.
Two op-amps are needed per battery cell, but they are cheap. The only per-cell "precision" part is R1, which should be equal to R5. 0.5% resistors would reduce the gain error to be on par with op-amp offset errors, and certainly a couple times smaller than the errors you had before. Op-amps with tighter offset specs, like LM324B or LM2904B, would further improve matters in that regard.
Settling after channel changes would be limited mostly by op amp slew, since no op-amps would be running open-loop at any point.
R10-D1 shifts the battery ground up relative to op-amp ground by about 5V.
For higher (+) terminal cell voltages, the OA1-OA2 circuit would be still used with each cell, but it would be supplied from supply rails shifted about 14V higher. The switched capacitor circuit below could do it.
simulate this circuit
R2 should be adjusted to be about 10% lower than the value needed just so that VSS won't be dipping below 14V. It likely will be higher than shown, since neither C1 nor C3 charging current flows out of C2.
When 555's OUTPUT is low, C1 charges to above 19V through D1 and U1's low-side output transistor.
When the OUTPUT is high, C1 is connected parallel to C3 via the diode D1 and U1's high-side output transistor.
D3 carries the return supply current of the op-amps supplied from VDD-VSS.
Finally, assuming that the 20V supply is not derived from the battery, the solution given here presents rather high impedance to the cell stack. The series resistors R2 and R3, in series with OA1 and OA2 non-inverting inputs, respectively, should give plenty of protection to the op-amps when fault conditions arise, such as an open cell, etc.
M1 could use a 10-15V Zener diode from gate to source, to prevent exceeding the rated gate-source voltage of M1.
There are much better ways of doing all this with modern parts, but if you want to limit yourself to cheap parts that will be available almost anywhere in the world - this would be one way to do it. M1 can be most any small signal PMOS device, by the way. It's not super-critical. It could even be an NPN transistor rated for high beta at 100uA - it would increase the error to 1-2%, not more.