How to control the transient output current of a synchronous buck converter?

Question

I am dealing with the following problem,

I want to control the output current and voltage of a synchronous buck converter during the output load (resistor) step change. Suppose we set the output reference current to a specific value. A step change in the load due to capacitor parallel to it, will result in a current spike (the voltage across the cap stays the same when the resistor value is changed (so the current spikes)). In my design i try to match Vout and Iout with Iout = f(Vout) according to a function f.

To be more specific, when a load R1 is connected to the buck's output the Vout1 and Iout1 will get their values such that Vout1/Iout1 = R1. If I change the R1 to R2 (suppose R2 > R1) the new values Vout2, Iout2 will set accordingly.

There is a also a need to control the transient response of Iout and Vout during a load change, so they will follow the function f from a steady state point at R1, to the R2. So my question is,

Is it possible to develop a control strategy to control these current and voltage transient responses ?? (I try to change the output LC filter to something like LCL, and working on the stability and the control design but only VOID is what I see)

Answer 1

Is it possible to develop a control strategy to control these current and voltage transient responses ?

Negative feedback is usually the way this problem is solved in DC DC conveters. In short: if the voltage is too high on the output, then swtich less. Conversely if the voltage output is too low then switch more.

Negative feedback requires more calculation then simply providing it to the DC DC converter. Stability of the feedback loop must be considered (and all parasitic of the power feedback path and the characteristics of the switch) which means applying control theory to DC DC converter design. If the loop is unstable it could result in the voltage output becoming unstable, and destroying the converter and/or load.

Answer 2

This step response is related to load regulation error which is the ratio of voltage error is due to the ratio impedance of source and load over some spectrum.

The closed loop bandwidth excess gain will attenuate this load regulation error with the best case at DC where it is specified.

The worst case depends on the ESR ratio with transmission line ringing effects and gain margin over the time interval of amplifying this low ESR voltage error and to correct it before the storage decoupling caps deplete.

These two causes are tradeoffs to final ripple specs. Imagine a 0 ohm ESR cap would delay the detection of the surge load/unload until it has sagged then you have loop latency. Then imagine you have standard or "high" ESR caps for the RC time constant that is shorter than the negative feedback loops reaction time.

In between these two times lies the critical lead/lag compensation or pulse to pulse sensing load regulation types of solutions that determine gain/phase margin, load regulation error and step load under/over shoot with steady-state ripple.