# Can I avoid buffering an analog sensor to ADC if I don't know its output impedance?

I am designing an analog input circuit for a pressure sensor with voltage levels of 0.5-3.5VDC. The initial intended circuit for this sensor is the following:

simulate this circuit – Schematic created using CircuitLab

The reference manual for the datasheet of stm32f401 designates max. Radc of 6k and max. Cadc of 7pF. The process variable is pretty slow, hence the ~150Hz cutoff frequency for the low pass anti-alias filter in front of the analog input. The MCU datasheet does not mention the min. Radc but I managed to find that, according to ST officials, it is 1.5k at 3.3V power supply.

According to the sensor's datasheet, it requires a load resistance above 10kOhms. Therefore I chose a 20k resistor in series with the ADC to avoid any peak currents that might fry my sensor's analog input driver. Unfortunately it does not mention anything about its output impedance. From my understanding the sensor driver should have a relatively low output impedance considering its required load resistance of 10k. Therefore I ignore the output impedance, however I am not 100% sure and your opinion would be helpful on this matter. If the output impedance turns out to be much larger I guess I would only experience changes in my cut off frequency which is not that serious as long as it is in the range of 30-150Hz. The measured process has a very slow dynamic therefore I can accept such low range of my low pass filter. I'd be very grateful to learn if you see any additional problems that might arise due to a high output impedance of the sensor?

Given the sensor's accuracy of 3% from the full scale range it can only measure as low as 4bars*0.003 = 0.12 bars, which is 0.12/4*(3.5-0.5) = 90 mV. With my 12 bit ADC with 480 cycles of sampling time at 10.5 MHz, I can measure as low as: $$Vadc_{level} = \frac{Vref}{2^{N-1}} = 1.6 mV$$

The voltage drop that would appear at the C1 capacitor due to ADC switching would be: $$Vdrop = \frac{Vin*Cadc}{C1+Cadc} = 0.46mV$$

which means I can avoid any ADC distortion due to slow charge of Cadc. Even if there is something, I believe I can still filter it out with a low frequency digital filter, which I intend to use in order to filter out 50Hz frequency noise from nearby power lines. I know that 21 KSPS for my ADC is quite fast for my sensor dynamic, but this is as slow as I can go since the ADC clock is shared with my SPI which requires 40MHz speeds. It also gives me the freedom for the number of samples I can use in my window average filter.

Remarks:

1. Please note that I don't use any ESD protection because the sensor will be connected in a controlled ESD proof environment
2. The sensor is powered by 5VDC LVR and I believe that it should not exert any high voltages that may damage the ADC. Your opinion on this would also be helpful. Maybe I should buffer the signal in order to avoid unexpected high voltage spikes from the sensor's driver?
3. I am aware that the 3.5VDC range of the sensor exceeds my Vref of 3.3V, in spite I have decided to ignore it. You can find more information regarding my decision on this thread.
• If the sensor specifies a load impedance of 10k or greater, and you're respecting that limit (which you have), then the voltage output from the sensor should be correct aka within it's accuracy specs.
– Drew
Jul 14 at 17:37
• I’m guessing here that the 10k max load is specified in ‘characteristics’ rather than ‘abs max’, so there’s little sander is damaging the device. Since the ADC is essentially a capacitive load, I think you’ll find that eliminating the series resistance will give you a faster settling time and improved accuracy. The ADC’s input resistance is in series with its capacitance and not a DC path to ground, which would affect the sensor’s output voltage.
– Frog
Jul 16 at 23:49
• @Frog the datasheet is very limited. There are no any abs. max specs, so I can't say for sure. Jul 17 at 10:36
• Are you sure that R1 does not need wired to ground ? Jul 17 at 15:50
• WHen there is uncertainty, you breadboard and test Jul 23 at 1:47

I think buffering samples is not mandatory, however interresting if "long wires" are used.

For evaluating your needs, I have made 2 simulations (microcap 12) at slow speed signals ( triangle). I changed also a little the sensor resistor configuration. See the "delay" when the value of C1 is too high. I have reduced (R1 & R2 divider) the voltage output to be "compatible" with 3.3 V, may be changed. Time sample pulse is as large as "sample and convert" occurs. May be changed.

Sampling error of "capacitive loading" is "low" but predictible as 50 nF are quasi ~ 7 000 times 7.5 pF. Added also a large view near sample to see what happened ...

I have changed C5 to 5nF. At the (Vs) slew rate used for test, the "error" (Vm versus Vs) of sampling is 10 mV. Error will be lower if Vs slew rate is lower ...

• I believe you are trying to say that this is how you would have implemented it if you were using this sensor? I just wanna correct the sampling time. It's not 12+3 cycles, it's 12+480 cycles since I'll have the SAMP register adjusted for it. I also have a remark on the RC filter here. I believe the cutoff frequency will be 530Hz here considering the added voltage divider. In other words the capacitor will be connected to a series resistance of R1*R2/(R1 + R2) Jul 18 at 17:33
• Yes for the cutoff frequency. Not calculated. "the capacitor will be connected to a series resistance of R1*R2/(R1 + R2)" ... Yes. And sensor will be terminated on a resistor load of R1+R2 > 10 k. For sampling time ... I made an error ? Ok. I correct the sampling time. What is your clock ? Jul 19 at 7:17
• @Phill Donn Newer simulation with ~ 10us sampling time. Jul 19 at 7:42
• @Antonio51,May i know which is this simualtor
– Hari
Jul 29 at 9:37