I've preparing for Physical Design Interview and came across couple of explanations that deduce that the delay of logical gates will increase once we reduce VDD. what is the reason?

my intuition sends me to the famous equation Q=CV. supposing Q is still constant, if V is reduced then C will go up, thus increasing the RC delay.

is this the right explanation?


Most of these circuits are CMOS, particularly if they support a wide range of supply voltages. In a MOSFET, the higher the difference between the gate and source voltages, the higher the current that transistor will pass.

When you reduce VDD, the drive voltages on the gates are reduced, and the amount of current they pass is reduced. CMOS loads are largely capacitive, so the amount of current you deliver directly affects the rate at which that node can change voltage...hence, the circuit is slowed down. Most circuits in ICs have several layers of combinational logic between state elements, so the slowdown compounds with each layer.


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