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Ok this is probably a basic question, but I understand how SR latches work except one thing.

In the R input and S input you can make them 0 or 1.....but what about the input lines next to them (That rely on the output of the R or gate or S or gate)......what do those "Start" out as.

I assume it's Zero.....but with the very first clock signal (To R or S)....it hasn't gotten the output line from the other OR gate yet...so how can it get a first output.

Like lets pretend the first clock signal is R=1 and S=0 ....what about the R or gates input line next to it (that relies on the S OR gates output).....how can it get this on the first "input" signal. It confuses me?

Do we just assume it's zero or what?

edit: Since the question is confusing, the Input line RIGHT below the R (They both go into the top OR gate, im talking about the one right below it). Since it is dependent on the S output....if it's the first "Clock" signal...what would it be set to? Zero? Since obviously it has to wait for the output of S before it can actually be set to anything...but initially what is it considered.

enter image description here

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2 Answers 2

Reset to default
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They start out undefined, that is they could be set to either.

When you switch power on, assuming a real latch with no input signals, both gates will want to output high. However due to no two gates being exactly the same (and other real world effects), one will "win" the race to bring it's output high first, and set the others output to low. The same gate may not win every time, so you can't predict the state at power on.

This diagram (from the second link below) helps to visulalise things:

Metastable condition

For further reading about this and metastability, see these links:

Wikibooks SR latch
Latches and FFs
Wiki Metastability
Metastability document

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  • \$\begingroup\$ I think my question might've been misunderstood. Im not talking about R or S, im talking about the input line next to it. Like The OR gate R is attached to, the line right below it...the input depends on the output of the OR gate S is attached too..if it's the first signal what is the second line (below the R) considered? or maybe im confused at your answer :P \$\endgroup\$
    – user3073
    Commented Feb 10, 2013 at 5:27
  • \$\begingroup\$ Yes I understood - I'm referring to the outputs/second input of each gate also. If you imagine they were not connected, then on power up both gates would output high (assuming R and S are low). However if they are connected, then both outputs being high at once is not possible. So one has to "get there first", but we don't know which one it will be, so we consider the state of the latch (i.e. either of these other inputs) to be undefined at power on. \$\endgroup\$
    – Oli Glaser
    Commented Feb 10, 2013 at 6:31
  • \$\begingroup\$ @Sauron - I added a few links that may be worth a read. \$\endgroup\$
    – Oli Glaser
    Commented Feb 10, 2013 at 6:54
  • \$\begingroup\$ The lines next to the inputs are the outputs via a feedback path. If you can't guarantee output state, you can't guarantee these either. \$\endgroup\$
    – Scott Seidman
    Commented Feb 10, 2013 at 13:48
  • \$\begingroup\$ Ok Quick question then.....Can a signal still go through an OR gate without the other one connected. (Like could voltage still go through the line R if the one below R hadn't been reached yet?) and you said they'd automatically output to High assuming S and R are low) Why is this? \$\endgroup\$
    – user3073
    Commented Feb 10, 2013 at 17:55
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That's the thing with memory devices like flip flops -- you need to initialize them. You can't assume anything about the startup state. If its important to the functionality of your circuit, your power on routine must assert one of the inputs to guarantee a known state.

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