'High Impedance' in this context means that the SO (chip data out) line is not being driven by the chip. This is represented in the diagram as a line at mid-level. In reality the SO pin is floating; the actual signal state is undefined and can't be counted on as a valid logic level.
Good system design will ordinarily resolve this by adding a pull-up or pull-down to the SO line, so that it will not be floating when it's undriven. If it's a pull-up the SPI host will see the incoming SO 'high-impedance' time as all 1's on its MISO/DIN pin.
For the example read command shown, with a pull-up on SO (host MISO/DIN) you will see the raw sequence FF FF FF FF, followed by the data bytes. The host SPI controller might be programmed ignore these bytes (e.g., with a 'read latency' setting), or they can be discarded by software.
Why do they do this? It allows multiple SPI devices can share the same host MOSI and MISO pins, each one being selected by its own CSn pin from the host. In a multi-chip SPI system, only the device activated by its CSn pin will drive the host MISO line, the other unselected devices will remain in high impedance.
A quick SPI nomenclature note:
- MISO/DIN = Master In, Slave Out. Connects to device SO
- MOSI/DOUT = Master Out, Slave In. Connects to device SI