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Question is the following:

lets say that all interfaces a modules are defined correctly:

module SOCKET (RD_IF rd_if, WR_IF wr_if, input ... /* list of common connections */); 
   
   RD_IF rd_if_socket;
   WR_IF wr_if_socket;
   
   SOCKET_RD read_socket_module(rd_if_socket);
   SOCKET_wr write_socket_module(wr_if_socket);


   assign rd_if.A = rd_if_socket.A;
   ... // THis is painful way to make these connections
endmodule

SO the Question is how do the do the above connection of an instantiated interface inside a module to the interface defined in the module port list -- without doing it the tedious way of one connection at a time.

The reason I need to do this is because the SOCKET_RD/WR both share common signals that I would like to only connect once (instead of doing the connections twice to both modules in the TOP)

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Currently Systemverilog does not allow assignment of one interface instance to another (ex. IF_A_1 = IF_A_2). So an instantiated interface cannot be connected to an interface defined in the module port list without doing the connection by hand, one variable/wire at a time.


An alternative is thinking of an interface as a single backplane that you make connections as a whole, and your sub-connections using a modport. The interface IS the connection, not something you make connections to.

module SOCKET (SOCKET_IF sif); 
  SOCKET_RD read_socket_module(sif.RD_IF);
  SOCKET_WR write_socket_module(sif.WR_IF);
    
endmodule

interface SOCKET_IF;
  bit clk, reset;
  // RD signals here
  wire rwire;
  logic rlogic;
  // WR signals here
  wire wwire;
  logic wlogic;
  modport RD_IF(inout rwire, output rlogic, input clk, reset);
  modport WR_IF(inout wwire, output wlogic, input clk, reset);
endinterface

module SOCKET_RD(SOCKET_IF.RD_IF rd);
   ...
endmodule
module SOCKET_WR(SOCKET_IF.WR_IF wr);
   ...
endmodule
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  • \$\begingroup\$ Hey Dave, nice to see you here, so this would fix the issue of connecting the common signals to the WR/RD sockets inside module SOCKET, but to connect rd_if/wr_if to the instantiated interfaces (rd_if_socket/wr_if_socket) is still the larger issue here as that takes quite some time \$\endgroup\$ Jul 19, 2021 at 18:19
  • \$\begingroup\$ yes, this is a great workaround \$\endgroup\$ Jul 20, 2021 at 15:43
  • \$\begingroup\$ I would say remove the first part, as it is not relevant to the question, and add a small snippet about the original question (can you assign instantiated interface to module port interface), basically saying that it is not possible, and here is a workaround..., then I would be happy to accept. I would be happy to edit it myself, it you don't mind... \$\endgroup\$ Jul 20, 2021 at 15:51
  • \$\begingroup\$ It's a great alternative, the modport option \$\endgroup\$ Jul 20, 2021 at 16:28
  • 1
    \$\begingroup\$ verificationacademy.com/forums/systemverilog/… -- leaving this here for anyone who wants to see a longer discussion on this matter \$\endgroup\$ Jul 20, 2021 at 19:35

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