# Are there two sorts of *geometry* of JFET?

• In some schematics of JFET, we see in the geometry that the source and drains are perpendicular to the position of the gate.

Example : https://en.wikipedia.org/wiki/JFET

• In some schematics of JFET, we see in the geometry that the source and drains are parallel to the position of the gate.

Are there two sorts of geometry of JFET?

Also, some schematic (as the first one) schow one gate. Some schematic (as the second one) show two gates: the channel is taken in sandwich. Are there two additional geometries for this point?

• I doubt the first diagram is representative of an actual JFET. Jul 18, 2021 at 20:37
• Please note that plenty of references show example of the first diagram. Example : fr.wikipedia.org/wiki/Junction_Field_Effect_Transistor , electronicspost.com/… , youtube.com/watch?v=A0NGvfP4ABU , clearconc.blogspot.com/2019/11/… , so if this is a wrong schematic, plenty of people say something completely wrong. Jul 18, 2021 at 20:56
• Who said anything about it being wrong? It just means it's a "lie to children". Just like diagrams of motors. Look a a motor diagram, then look at an actual at an actual motor. Jul 18, 2021 at 20:56
• @MathieuKrisztian It's not wrong--that construction would work, and is simple to explain. It's just not the best way to build a JFET. Jul 19, 2021 at 15:01

The first sketch shows the principle of a JFET (in a way that is easy to analyze mathematically). The general concept (in any JFET) is that the depth of the conduction region (between S and D) gets reduced as gate bias increases (becomes more negative).

The 2nd sketch is how a JFET is actually constructed, although most JFETs don't have a gate underneath the device also. In addition the depletion region doesn't have the 'wobbles' shown.

• Are there JFET that have a gate underneath the device or is it an invention from the authors of illustration ? Jul 19, 2021 at 6:22
• Presumably, the gate doped region is underneath, but the ohmic contact of the metal electrode to it is still at the top (and the doped region reaches the surface at that spot), unlike how it's pictured. Jul 19, 2021 at 15:42
• Power MOSFETs in an integrated circuit (called LDMOS) basically consist of a low voltage MOSFET with a JFET in the drain (that's how it sustains voltages as high a 600 V or more). That JFET is sometimes depleted from both sides, but there is not an accessible or separate gate terminal for the JFET. Jul 20, 2021 at 0:46

From National Semiconductor Discrete Semiconductor Products Databook 1989, an illustration of top-contacts of the N-channel FET (process 55) suggests that the gate does go underneath.
This illustration only shows top-metallized regions, and does not show variously-doped regions. But it does show the top-view geometry.
FETs with lower $$\RDS_{ON}\$$ often have more interdigital fingers, and higher capacitances.

A backside gate connection seems fine for a single, monolithic JFET. But what about multiple JFETS?...or FETS integrated into an IC like an opamp?
A similar dual-FET (process 83) seems to be made monolithically on the same substrate. National claims that the substrate is "diode isolated":

You're looking at two drawings and assuming they're factual

While the first drawing is a simplification for the purpose of showing basic structure and operation and the second diagram is more complete with substrate effects and doping diffusion (even it's not "complete"), the problem here is that you're looking at images in a book and assuming they represent very different things.

Why would you assume that? Not meant to be an offensive question, it's just odd that you do.

In reality, there's nothing stopping a manufacturer from building a silicon cube and plopping a gate on all six sides — in which case you could "factually" claim that JFETs are manufactured in vertical, horizontal, right-side-up, and up-side-down configurations — but in reality there's just the one type of JFET.

It's worth noting that there are many ways to build a JFET just as there are many ways to build a car. Back when I was designing, it was common to create interdigitated FETs (the gate was built as two parallel strips of SiO2 drawn like your two hands with fingers spread apart and brought together so the fingers of each hand overlapped). That minimized the capacitive charge required to actuate a very large FET. We also had FET designs that looked precious next to nothing like a regular transistor that were used for ESD discharge circuits and the active loads on current sources.

Don't get too hung up on how things are drawn in books. Unless specifically told otherwise, assume they're different ways of showing you the same thing for the purpose of highlighting specific concepts.