Are there two sorts of *geometry* of JFET?

Question

• In some schematics of JFET, we see in the geometry that the source and drains are perpendicular to the position of the gate.

Example : https://en.wikipedia.org/wiki/JFET

• In some schematics of JFET, we see in the geometry that the source and drains are parallel to the position of the gate.

Example : https://www.electronics-tutorials.ws/transistor/tran_5.html

Are there two sorts of geometry of JFET?

Also, some schematic (as the first one) schow one gate. Some schematic (as the second one) show two gates: the channel is taken in sandwich. Are there two additional geometries for this point?

Answer 1

The first sketch shows the principle of a JFET (in a way that is easy to analyze mathematically). The general concept (in any JFET) is that the depth of the conduction region (between S and D) gets reduced as gate bias increases (becomes more negative).

The 2nd sketch is how a JFET is actually constructed, although most JFETs don't have a gate underneath the device also. In addition the depletion region doesn't have the 'wobbles' shown.

Answer 2

From National Semiconductor Discrete Semiconductor Products Databook 1989, an illustration of top-contacts of the N-channel FET (process 55) suggests that the gate does go underneath.
This illustration only shows top-metallized regions, and does not show variously-doped regions. But it does show the top-view geometry.
FETs with lower \$RDS_{ON}\$ often have more interdigital fingers, and higher capacitances.

A backside gate connection seems fine for a single, monolithic JFET. But what about multiple JFETS?...or FETS integrated into an IC like an opamp?
A similar dual-FET (process 83) seems to be made monolithically on the same substrate. National claims that the substrate is "diode isolated":

Answer 3

You're looking at two drawings and assuming they're factual

While the first drawing is a simplification for the purpose of showing basic structure and operation and the second diagram is more complete with substrate effects and doping diffusion (even it's not "complete"), the problem here is that you're looking at images in a book and assuming they represent very different things.

Why would you assume that? Not meant to be an offensive question, it's just odd that you do.

In reality, there's nothing stopping a manufacturer from building a silicon cube and plopping a gate on all six sides — in which case you could "factually" claim that JFETs are manufactured in vertical, horizontal, right-side-up, and up-side-down configurations — but in reality there's just the one type of JFET.

It's worth noting that there are many ways to build a JFET just as there are many ways to build a car. Back when I was designing, it was common to create interdigitated FETs (the gate was built as two parallel strips of SiO2 drawn like your two hands with fingers spread apart and brought together so the fingers of each hand overlapped). That minimized the capacitive charge required to actuate a very large FET. We also had FET designs that looked precious next to nothing like a regular transistor that were used for ESD discharge circuits and the active loads on current sources.

Don't get too hung up on how things are drawn in books. Unless specifically told otherwise, assume they're different ways of showing you the same thing for the purpose of highlighting specific concepts.