Verilog non-blocking assignments

Question

Consider the following Verilog snippet:

module mod1 ( input clk, input [1:0] a, input [1:0] b, output reg [3:0] c); 
 always @ ( posedge clk)
  begin 
    c <= {c, &a, |b};
    c[0] <= ^c[3:2];
  end
endmodule

In my textbook it says

A group of blocking assignments are evaluated in the order they appear in the code, whilst a group of nonblocking assignments are evaluated concurrently, before any of the statements on the left hand sides are updated.

So what does that mean here? Suppose c = 1100, a = 11 and b = 01 at the beginning. The first statement will read as c = 0011 and the second as c[0] = 0 because the c in the second statement is 1100 since the assignments only take effect after the clock cycle if I understood the textbook correctly. But what is c in the end? Is it 1100 because of the last statement, or is it 0010? Please also explain why.

Answer 1

Both statements assign a value to c[0], so even with nonblocking assignment, it is the last statement that prevails. This means that |b in the first statement is discarded, and the result will be 0010. The first three bits come from the first statement, and the last bit comes from the second statement, all updated simultaneously.

It could be written as a single, less confusing statement:

c <= {c[1:0], &a, ^c[3:2]};