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Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that the CPU will have some levels of cache directly on it, but I'm curious where the main memory is.

If not the architecture, what do existing RISC-V CPUs do? Do SiFive's CPUs store the RAM on the same chip as the CPU, or elsewhere on the board? Is it generally better to do one or the other? Does it depend on how the architecture is designed? I found this question but the answers seem to be focused on desktop x86 and POWER CPUs.

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    \$\begingroup\$ Just like ARM, it comes down to the actual implementation. The core itself exposes a memory interface. Cache is optional. On the GD32VF103 device i have, the memory is on chip with the core cpu. \$\endgroup\$
    – Kartman
    Jul 20, 2021 at 4:44
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    \$\begingroup\$ RISC-V specs talk about ISA mostly and the register file but not the whole SoC hardware architecture. That's implementation specific. SiFive should have their own implementation. So you should check their open cores in GitHub or so. RAMs are off-chip (outside processor) in almost all SoCs. \$\endgroup\$
    – Mitu Raj
    Jul 20, 2021 at 6:34
  • \$\begingroup\$ The only ARM SoC I can think of that has integrated DRAM is the Apple M1. \$\endgroup\$
    – Oskar Skog
    Jul 20, 2021 at 7:13
  • \$\begingroup\$ Some of the raspis had dram as PoP (package on package) and there’s many others that have dram integrated - Allwinner V3s, nuvoton, Atmel ........ \$\endgroup\$
    – Kartman
    Jul 20, 2021 at 13:40
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    \$\begingroup\$ There are also x86 CPUs with all RAM on the chip (Intel Quark) and ARM devices with RAM on the motherboard (Amazon Graviton). ISA doesn't determine where the memory is, how much RAM you need and how much you want to pay determines that. \$\endgroup\$
    – user1850479
    Jul 20, 2021 at 16:52

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RISC-V is not a CPU, it's an Instruction Set Architecture (ISA). ISA only specifies the instruction set and some registers. ISA does not specify where the Memory should be located, which is a matter of hardware implementation.

The goal of ISAs is to enable binary compatibility between 2 processors that implement the same ISA, even if they use different microarchitectures / hardware implementations. In RISC-V ISA, there are different extensions like 32-bit, 64-bit, bit-manipulation etc.

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    \$\begingroup\$ I never claimed RISC-V is a CPU, I said "RISC-V CPU", meaning "a CPU with the RISC-V ISA". But thanks for the answer. \$\endgroup\$
    – Aaron Franke
    Jul 21, 2021 at 3:25

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