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Does I2C have any data loss prevention mechanism? If so, how does I2C recover?

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    \$\begingroup\$ It has ACK/NACK mechanism. Based on it the data might be retransmitted, but it is up to the peers. \$\endgroup\$
    – Eugene Sh.
    Jul 20 at 15:06
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    \$\begingroup\$ The idea behind I2C is to keep things simple. Adding error correction would complicate things and adding I2C to a simple/cheap IC would not be cost effective anymore. So instead we EEs implement I2C such that it is robust and data loss practically doesn't happen. If you want I2C with error correction then you should consider using a more advanced protocol instead. \$\endgroup\$ Jul 20 at 15:08
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    \$\begingroup\$ What kind of data loss mechanism do you mean? Like, what if a chip is missing so transaction can't start? Someone removes a chip during a transaction? Someone sends too few or too much bits/bytes? \$\endgroup\$
    – Justme
    Jul 20 at 15:25
  • \$\begingroup\$ Not about chip missing.I was indicating to the fact that what if some bits get changed /while being transmitted.Is there any error detection method for that?@Justme \$\endgroup\$ Jul 21 at 15:54
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I2C has several mechanisms to prevent data loss:

  • multi-master collision detection and arbitration
  • ACK/NACK after each byte
  • clock stretching (slave slows down the master)

SMBus adds a couple of enhancements:

  • Packet Error Check (PEC), a CRC sent after each transfer
  • limits on clock stretch and maximum clock period
  • time-out to prevent bus lock-up

Taken together, these mechanisms can be built upon to make robust I2C communications in single-master or multi-master systems.

There is however no built-in mechanism in I2C or SMBus to guarantee delivery of data. That level of error recovery would be implemented at a higher level. It is up to the driver and application to monitor I2C transactions and determine what to do if an error occurs, be it I2C or SMBus.

Is it possible to implement a guaranteed-delivery protocol over I2C? Sure, with some work. I see references / requests for PPP over I2C for example, which would use TCP/IP layered on top of the link.

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  • \$\begingroup\$ Thanks.Lets say a bit is toggled while being transmitted.Does the receiver has any way to detect it?As far as I know,ACK pin becoming logic 0 only ensures that 8 bits have been received . \$\endgroup\$ Jul 21 at 16:04
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    \$\begingroup\$ There’s no low-level way for I2C to detect that kind of event by itself. There’s no parity or ECC for example. This would have to be handled at the higher level. SMBus could detect some errors using its packet error code. \$\endgroup\$ Jul 21 at 16:07
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It doesn't. If you want error correction, you have to implement your own error-correcting code.

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I2C does not provide any means of error checking as it was originally intended to communicate between components on a single board where the probability of error is very low, the acronym I2C actually stands for Inter-Integrated Circuit.

However, since its inception, I2C has been used for many applications and has been extended in capability. One of those extensions is called SMBus (System Management Bus). It is backward compatible with I2C but does provide a mechanism for error checking referred to as PEC (Packet Error Checking) where a CRC can be added to the data packet. It also supports a timeout mechanism to avoid bus lockup that can occur with I2C.

System Management Bus

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The worst-case comm. errors are lockup conditions such as when a clock pulse was missed and the sender keeps the data bit active. The receiver could reset, but the sender doesn't know.

There are many scenarios of lock-up, so the system design must ensure there is a recovery mechanism.

  • always implement a well-defined time-out period when waiting for any I2C event
  • if a time-out occurs, either reset all the slave devices or issue a sequence of at least ten clock cycles on the I2C SCL signal (one more than a byte transfer)
  • it might be handled by software or hardware.

Communication errors usually exist due to hardware design faults from inadequate EMI protection or unexpected interference. They are intended to be used in simple IC to IC channels in a safe environment.

Proper EMI design from the environment can be simple with guarding ground tracks or planes and adequate pull-up current but risk of interference increases with length and lack of awareness of impulse noise.

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