VHDL and Verilog were originally designed as languages to describe hardware for simulation. They were later re-used as languages to describe hardware for synthisis.
There are two strategies to describing hardware, behavioural and structural. In behavioural description we use program code to describe how our hardware behaves. In structural description we describe our peice of hardware in terms of smaller peices of hardware.
Most practical designs will use a mixture of both. So you have small behavioural blocks (always blocks in verilog, processes in VHDL) within an overall structural design.
Normally we have two main types of behvaioural block. "combinatorial" blocks define a combinatorial function of their inputs. Logically they are run when any input changes and they have no memory.
Sequential blocks are normally written to define what happens after the clock edge in terms of what happened before the clock edge. This is how we manage to maintain a determinisitic design even though all blocks triggered by the same clock edge run in a nondeterministic order in the simulator and at the same time in the synthisized hardware.
If you plan to synthisize your code then you need to think about what things mean structurally even when defining them behaviourally, because the first thing the synthisizer is going to do is translate your behavioural description to a structural one. Loops will be unrolled, arithmetic and logic statements will become arithmetic and logic hardware blocks. Flow control statements will become multiplexers (potentially very wide ones).