1
\$\begingroup\$

I am building a custom D flip flop in Logisim as a part of the project for my computer organization course and I am not allowed to use the built-in flip flops. When I designed this flip flop everything went well and every wire and connection was green and there was no error, however, when I reset the Simulation or try to use the circuit as a single component in another circuit, the problem shows up, and some of the internal wirings turn to red including outputs. Does anybody know a solution to overcome this problem? thanks in advance. Sorry for the bad English. Initial State

After resetting simulation

as a single component

\$\endgroup\$
8
  • 1
    \$\begingroup\$ You didn't hook up the "clear" input to anything, and the "enable" input is tied to ground. Until the FF is cleared, the simulator can't resolve the state of the red nodes, so they remain in an "unknown” state. \$\endgroup\$
    – Dave Tweed
    Commented Jul 21, 2021 at 10:05
  • \$\begingroup\$ I assumed if no pin is connected to a pin, its state will be the same as the value shown in the circuit since I couldn't find any documentation about this behavior on Logisim's main website. And Since I'm a computer science student I don't know anything about "the ground" so could you please clarify more on that? thanks \$\endgroup\$
    – Milad5608
    Commented Jul 21, 2021 at 10:30
  • \$\begingroup\$ @Milad5608 tied to ground means it is 0. Your enable is 0, so the circuit is not enabled. \$\endgroup\$ Commented Jul 21, 2021 at 10:34
  • \$\begingroup\$ @Milad5608 if a pin is not driven, it will be unknown. \$\endgroup\$ Commented Jul 21, 2021 at 10:35
  • \$\begingroup\$ @ShashankVM enable input is meant to be 0 because I want to control flip flop's input and enable it based on a control function. Thanks for the clarification on pin states. \$\endgroup\$
    – Milad5608
    Commented Jul 21, 2021 at 10:37

1 Answer 1

0
\$\begingroup\$

You need to connect the clear input to the gates from which you get the outputs Q and Q'. When clear is pressed, Q = 0 and Q' = 1 for proper operation of the flip-flop.

An easier option would be to have a single output Q, and generate Q' from Q by connecting Q to a NOT gate.

Without clearing the flip-flop, the previous state would be unknown. In some situations, this unknownness of the previous state propagates to the following states, and the output remains unknown. Hence use a proper clear input to clear the flip-flop before testing other inputs.

Your problem is the same one described here:

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.