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I have a circuit with a not-so-small capacitor on the supply and I need to reduce the inrush surge; as a matter of fact the power supply breaks after a while (these cinese supplies are not fun)

I followed ON Semi AND9093/D (which is in fact very well made) and come up with the following circuit:

Test circuit

From the left comes a 12V supply, on the bottom there is a BJT enabling the switch when the times come and on the right after the beefy capacitor there a mixed load; at the moment is still disabled but there's some leakage anyway on the right side, if only for the capacitor one.

The circuit actually works quite well and limits the current as designed (5A, by the way): Load switch transient

However there is still a surprise: when I initially apply the supply there is still a surge while the load switch itself stabilizes:

Supply on transient

I explain this as follow:

  • At start up everything is discharged, C12 and C13 included;

  • When I supply power Q1 is in conduction even if /HSGRAIL is not pulled down since the source is at supply level and the gate is still low since C12 is not charged yet (probably some leakage from somewere make it starting low, even the /HSGRAIL has some leakage of course)

  • The gate initial charge to the supply is slowed down since C12 needs to be charged initially, too.

However if I lower R2 to raise the charge current, R3 need to go down to maintain the FET below Vth and then C12 would need to be bigger in proportion (the sad rule about RC time constant)

What would be the best way to solve this?

  • Some magic topology trick?
  • A push-pull gate drive (i.e. R2 and R3 replaced by transistors) so that it actually starts charged quickly? probably would need to make it discrete since most of the integrated ones stay high impedance until supply is stable;
  • Switch to an N-channel switch and a charge pump driver? (a lot more expensive but if it's the only way)

EDIT: I forgot the oldest trick in the book:

  • No gate-source capacitor.
  • A 'suitably big' charge resistor (refined people would want to use a inrush control NTC)
  • After some time bypass the resistor/NTC with the MOSFET to reduce losses (even when the cap is charged it will be need to be recharged)

22 ohm about 1W seems to do the trick, I'm doing tests

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  • \$\begingroup\$ Yes, C12 is the culprit because when it is discharged and you connect 12V, it will immediately turn on the P-FET until it is C12 is charged. Why it is between drain and gate, and why it isn't between source and gate? \$\endgroup\$
    – Justme
    Jul 22 at 7:32
  • \$\begingroup\$ I'm wondering the same, but the application note says it's better (because the miller plateu is bigger) and in fact in similar designs I usually see in that position. Even putting it on gate-source however would need time to charge it (maybe it would be faster but bigger to have the same control effect) \$\endgroup\$ Jul 22 at 7:36
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I would recommend using a dedicated soft start load switch IC, for example an NCP45524. The advantages (to my mind):

  • Low \$R_{DS}\$ N-Channel MOSFET, with a built in charge pump.
  • Controlled soft start.
  • Controlled discharge of the load when switched off.
  • Thermal protection.
  • Power good indicator.
  • Reduced BOM complexity and space usage.

Disadvantages:

  • May be more expensive (offset somewhat by reduced BOM)
  • Less likely to be able to directly substitute if the IC becomes unavailable or EoL.
  • Less intellectually satisfying, which may be a consideration for a hobby project :)
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  • \$\begingroup\$ In fact that was one of the proposals:P I already use analog/linear virtual diodes controllers in other projects so I'm aware of these. A big problem these days is that many manufacturers simply don't deliver (TI has parts at 74 weeks of lead time) so we have to do with what find \$\endgroup\$ Jul 22 at 10:35
  • \$\begingroup\$ @LorenzoMarcantonio - yes noted it was a proposal, thought I'd agree and why :) The lead time for everything just now is interesting; I included availability in the disadvantages. \$\endgroup\$
    – awjlogan
    Jul 22 at 10:38
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enter image description here

With this modification, VGS will be reduced initially, and will not influence when Enable goes to low value. It will affect when Enable goes to high value, I cannot simulate now.

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  • \$\begingroup\$ interesting, it warrants at least a spice try! \$\endgroup\$ Jul 22 at 11:14
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You could place a resistor or a current sink across DS of Q1 .Now the cap charges naturally .Set this up below your 5 amp peak .Hold off Q1 while this charging happens ,Then turn on Q1 .I have used a basic Vbe threshold to determine if the rails are close enough to turn on the mosfet .This approach means that mosfet turn on speed is not so crucial .I have also taken V rail to your load from the source of the P channel .These days RDs on should be low enough to not degrade the cap esr .

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