Usually the following configuration for unused opamps is said to be troublesome, even for rail-to-rail input & output (RRIO) opamps. Nevertheless, it is attractive because it requires no additional components.


simulate this circuit – Schematic created using CircuitLab

The reason seems to be anomalously high current consumpion due to output saturation. When the input offset voltage has the "wrong" sign, the output would need to go to a slightly negative voltage to reach equilibrium, thus saturating because it cannot achieve this.


What does this mean and why would it lead to increased current consumption ? After all, the only load on the output is a MOSFET gate which will not cause any appreciable current to flow. And all the internal gain stages are anyway operated with a constant supply current, no?

Another approach to formulate the same question is: Why is it deemed ok, to abuse such opamps as comparators, which almost always uses an open loop configuration and causes output saturation? Isn't this usecase equivalently "bad" as the one drawn above?

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    \$\begingroup\$ Is this about a specific op-amp, or in general? A specific op-amp may be used in a specific way in corner cases from how op-amps generally work. \$\endgroup\$
    – Justme
    Jul 23, 2021 at 7:35
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    \$\begingroup\$ @Justme no, not a specific opamp. It applies to all CMOS RRIO opamps. \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 7:37

3 Answers 3


The output stage of op-amps under saturated conditions may have a bit lower output current or significantly higher supply current than the datasheet promises as a maximum. The information on behavior with saturated outputs is not typically shown directly in the datasheet, but here is one reference.

Having the op-amp biased so it cannot balance could also lead to subtle interactions between the unused op-amp and the ones that are used- particularly at low signal levels such as mV. For example, I have seen such op-amps exhibit low amplitude but high frequency oscillation when the output is very close to the supply rail. That will be coupled to other amplifiers even at DC, but more so typically at higher frequencies (TLV4316 datasheet):

enter image description here

Ideally, create a voltage that comfortably allows the op-amp to balance at and connect it as a unity-gain buffer. For a RRIO op-amp that could be anything within the power supply range, save for a few hundred mV at either end. The voltage doesn't even need to be constant- it could be some signal-related voltage- you might be able to use it to buffer a test point or something along those lines.

You don't always have to follow the "ideal" recommendation, but if you have to ask it may be wise to do so.

Edit: Here is a general reference from TI on what to do with unused op-amps in a package.

  • \$\begingroup\$ Biasing the IN+ with resistors is what I wanted to avoid, But, duh.. you are right, obviously there is a perfectly in-range voltage available right nearby, namely at the used opamp. This can simply be connected to the IN+ and everything will be alright. Thank you \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 8:26
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    \$\begingroup\$ "The output stage of the op-amp will be something like class-AB so saturating it may lead to an increase in power consumption." I don't understand this. Doesn't saturation in this case correspond to basically class-D behavior ? I.e. the lower output FET will be fully on, the top one fully off. That way, no current would flow, even through the bottom FET, because the load impedance is basically infinite. At the same time, the output voltage would be well defined (= Ground). \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 10:43
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    \$\begingroup\$ @tobalt I'm going to retract that statement. The actual situation is fairly complex and individual op-amp designs may have power supply consumption that is somewhat lower with unloaded outputs at the rails or approaching 10x (and several times the specified maximum supply current) eg. OP184 with output high. The information is not typically shown on the datasheet. Thanks for raising that point. \$\endgroup\$ Jul 23, 2021 at 13:28
  • \$\begingroup\$ Thank you for adding that article. It contains very comprehensive information. Although it is still not clear from there, how the supply current increase could arise in a CMOS opamp, they demonstrate clearly that it can happen. They also confirm that abusing RRO opamps as comparators is equally bad. \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 13:39
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    \$\begingroup\$ I think the big difference here is that what OP has done with their op-amp is correct for a split rail supply configuration where GND is right between V+ and V-. They have single rail power to their op-amp, though, so the non-inverting input needs something intermediate between V+ and GND rather than being pulled straight to ground. \$\endgroup\$
    – J...
    Jul 23, 2021 at 15:52

The problem with the configuration you propose is that the input of the non-inverting, unity gain op amp is tied to ground, which is all the way to one extreme of the supply range.

Ideally, you should tie the input midway, you can achieve this with a resistive divider, the value of the resistor should be chosen so that input bias currents are not problematic - probably anything between 10 kΩ and 100 kΩ works well.

There are several reasons why tying the input to one of the extremes can be a problem. Perhaps your op amp is not rail to rail and cannot output 0 V, perhaps it does not support such a low common mode, perhaps the bias currents are supposed to flow into the chip, and this cannot happen from ground if ground is the lowest potential at the chip.

As you suggest, there are additional concerns. If the input offset is "the wrong way around", even a rail to rail input/output opamp will have a hard time because you are asking for its output to go below 0 V, which it cannot do. What happens inside the op amp is chip specific, but I imagine that high current consumption is a very likely outcome. Op Amps are built to work in closed loop configuration, with the inputs very close together, and asking the output to go below 0 V is the same as working in open loop. I imagine that there are several places inside the chip where such a condition would produce unexpected behavior which increases the bias current of the various stages.

  • \$\begingroup\$ Thank you for answering, although I believe most of what you write doesn't address the question, which is formulated after the 'Question' heading. I would also like to draw your attention in particular to the second paragraph in that section, which discusses the open-loop aspect. \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 10:53
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    \$\begingroup\$ I have seen the part about OL - why dod you think that abusing the opamps in open loop wouldn't produce the same result? \$\endgroup\$ Jul 23, 2021 at 12:15
  • \$\begingroup\$ I thought so, because exactly this scenario is often mentioned as things you can use the unused opamps for. Using half an opamp as a (rather slow) comparator seems to be a well accepted practise. However, I have never done this myself, so I cant comment if this leads to adverse affects such as current consumption. \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 12:17

OA’s have complex input structures and are not designed to perform well as comparators. The input impedance of protection circuits can significantly drop the input impedance making the input current the result of increased no load current with V diff input >>0. The datasheet must specify input limits that must be followed when unused as an output. Hysteresis might help with very high R values to limit input current to the Vcm load.

Linear mode is best for unused OA’s and be aware of unity gain instability for each type.

Rail to Rail OA’s are charge controlled high gain amplifiers that draw current for each transition based on the rate of change. When the output is steady with negative feedback, it has high gain but draws low current unless DC load current involved. When stuck at either supply rail , it is also low current and of course no voltage gain.

Either way is suitable for minimizing unused OA’s for low idle current with often 1uA/ch possible or less.

However floating inputs with stray negative feedback small leakage currents causes oscillations with higher internal losses that you want to avoid as well as interference to nearby high impedance active inputs.

Worse yet exposing the floating FET input to weak EMI crosstalk current and may result in failure from EOS input voltages on RRIO OA’s.

On misuse of RRIO’s as comparators.

RRIO’s with BJT common emitter complementary types are flawed for low current when saturated on outputs.

  • \$\begingroup\$ This is what I thought, too, but it is obviously wrong: please look in the link in the answer of @SpehroPefhany (first paragraph). Even CMOS RRIO opamp can draw significant current when railed statically despite having no load on the output. \$\endgroup\$
    – tobalt
    Jul 23, 2021 at 15:57
  • \$\begingroup\$ I see generalization is not true, just albeit for some like the analog.com/media/en/technical-documentation/data-sheets/… which are fine. So the “devil is in the details” so keep RRIO’s in linear mode and don’t use RRIO’s as comparators expecting to use rated micropower \$\endgroup\$ Jul 23, 2021 at 17:02

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