The MOSFET should have a maximum dV/dt rating in its datasheet. Multiply that rating with the FET's output capacitance to get the maximum allowed drain charging current. Any ESD current less than this current should not damage the FET and be dissipated via avalanche breakdown, which most FETs are rated to handle up to an often very large maximum energy.
Let's take the IRF1010E as an example: Max dV/dt is 4V/ns, output capacitance is 690pF typical. 4V/ns * 690pF = 2.76A. The Human Body Model's internal resistance is 1500 Ohms, meaning that a 4kV HBM ESD event (2.6A peak) will not exceed the maximum allowed drain dV/dt and should therefore not damage the FET.
If possible, adding a small capacitor from drain to ground will improve the ESD handling capability further. A TVS diode of course won't hurt either; however, the FET itself can act as a very effective voltage clamp as well due to avalanche breakdown, so an external TVS diode might be redundant. Keeping dV/dt under control is more important for the FET's survival, hence the capacitor.