CMOS Logic Gate Interpretation

So I came across this interesting question while researching CMOS logic gates: As is says, a logic function $$\Y\$$ is given and you are required to create a logic network that implements it. I am familiar with how to draw CMOS logic gates when given logic functions, but I am unsure how to interpret $$\Y\$$. From my understanding, say I wanted to draw the PUN first, I would need to solve for $$\Y\$$ in terms of complemented variables. Likewise, if I wanted to draw the PDN first, I would need $$\\overline{Y}\$$ in terms of uncomplemented variables (where the bar indicates a complement).

How would you interpret $$\Y\$$?

Can you assume that $$\Y=\overline{ABC+D}\$$? If this assumption is valid, then going through the logic gives $$\Y=(\overline{A}+\overline{B}+\overline{C})\overline{D}\$$, which I can draw a PUN for since $$\Y\$$ is now in terms of only complemented variables. The PDN could then be found via duality.

Another thought I had was to represent uncomplemented variables as double complemented variables (i.e. $$\A=\overline{\overline{A}}\$$ and so on) and solve from there.

• Since this looks like homework I will only give you hints. No, I don't think you can show, using Boolean algebra, that $Y = \overline{ABC + D}$. A "compliment" is something nice that someone says about you. The word you want to use is "complement". Beyond that, I don't think you have the correct procedure in mind. To find the PDN you want $\overline{Y}$ in terms of uncomplemented variables, because a high input to an NMOS transistor causes a low output. Jul 23 '21 at 18:45
• Working it in my head, if you only have non-inverted inputs available I think you'll need one inverter... and one way would be to calculate !Y, and then follow it with an inverter to get Y. De Morgan's theorem is your friend here.
– W5VO
Jul 23 '21 at 19:02
• Thank you for the responses! The more I work on the problem, the more I realize that inverters will be needed, since $Y$ can't be solved in terms of only complimented variables and $\overline{Y}$ can't be solved in terms of only uncomplimented variables. $Y$ and $\overline{Y}$ would have to be solved separately, since I now believe that duality cannot be applied. The PDN and PUN circuits would look fairly simple then, with inputs into the PMOSs and NMOSs being $\overline{A}$, $\overline{B}$, $\overline{C}$ and $\overline{D}$ as opposed to $A$, $B$, $C$ and $D$. Jul 23 '21 at 21:00

The initial assumption is inverted.

The use of all NOR functions in open drain inverters means shared pulling R’s might produce a simpler answer.

$$\Y=ABC+D\$$ as given

$$\Y={(\overline{A}+\overline{B}+\overline{C})}+ \overline{\overline{D}}\$$

Simple diodes shared are “wired OR” and shared open drains are “wired NORs”

Then you may choose the N or P types with complementary output bias for either state active low impedance 0 or 1 in this selection of PUN and PDN’s. Normally Nch with PUN’s were preferred for the output as Nch were slightly lower output impedance for the same chip size.

• Thank you for your response Tony. How exactly did you get the expression $Y=(\overline{A}+\overline{B}+\overline{C})+\overline{\overline{D}}$ ? If you double complement each variable, wouldn't you end up with $Y=(\overline{\overline{A}}+\overline{\overline{B}}+\overline{\overline{C}})+\overline{\overline{D}}$ ? Jul 23 '21 at 21:06