This is probably a silly question but I figured this might be worth another question instead of adding it onto my other one.
Referring to this question (About an SR latches first Q state) What is the beginning state for Q in a SR latch?
Lets pretend we have an AND gate (or really any kind of gate). Inputs with A and B and Output Y.
Now lets pretend I send a Signal to A and B. What is the Output of the gates Initial Value? Like is Y always set to 0? Like when the computer is first turned on?
Like for example a NAND is 1 when both inputs are zero......so we do always assume the NAND gates output is 1 like when we first turn on a computer, or it receives it's first signal?
or for instance lets say a NAND gate for instance, and I send a 1 through input A, and a 1 through input B.....lets say (for some reason) the A gets there faster.....is the output 0 for a second then switches to 1....or was it 1 before (since technically both inputs were zero before?)
I guess looking at the transistor diagram might make more sense, but I guess the "timing" of Gates and SR latches has me a bit confused at what the outputs are "initially set" to.