This is probably a silly question but I figured this might be worth another question instead of adding it onto my other one.

Referring to this question (About an SR latches first Q state) What is the beginning state for Q in a SR latch?

Lets pretend we have an AND gate (or really any kind of gate). Inputs with A and B and Output Y.

Now lets pretend I send a Signal to A and B. What is the Output of the gates Initial Value? Like is Y always set to 0? Like when the computer is first turned on?

Like for example a NAND is 1 when both inputs are zero......so we do always assume the NAND gates output is 1 like when we first turn on a computer, or it receives it's first signal?

or for instance lets say a NAND gate for instance, and I send a 1 through input A, and a 1 through input B.....lets say (for some reason) the A gets there faster.....is the output 0 for a second then switches to 1....or was it 1 before (since technically both inputs were zero before?)

I guess looking at the transistor diagram might make more sense, but I guess the "timing" of Gates and SR latches has me a bit confused at what the outputs are "initially set" to.

  • \$\begingroup\$ IMO this question shows some good thinking (with insufficient data to begin with, but that's what we are here for). So I upvoted it (removing a previous downvote). @All downvoters: leave a comment as to why you downvoted, you might even convince me you are right! \$\endgroup\$ – Wouter van Ooijen Feb 11 '13 at 13:09

We don't normally talk about a NAND gate having "state". It just responds to its inputs.

Since a NAND gate usually can respond to its inputs within a few nanoseconds, while power supply voltages typically take at least a few milliseconds to come up to valid levels during turn-on, the "state" of the NAND gates output immediately after start-up is rarely relevant.

In general during start-up there will be some time when the voltage rises to the point where the circuit is basically functional, but is not guaranteed to be functional. A NAND gate will start to respond to its inputs during this time and should be completely in sync with its inputs by the time the power supply voltage reaches the minimum voltage for guaranteed operation.

lets say a NAND gate for instance, and I send a 1 through input A, and a 1 through input B.....lets say (for some reason) the A gets there faster

This can happen, and it is called a "glitch". A typical case is when A is switching from 1 to 0 and B is switching from 0 to 1. The output to the prior inputs is 0, and the output to the final inputs is 0, but it's possible to see a 1 asserted for a brief time during the transition if the change in A arrives first.

This is why designing syncronous logic is in many ways simpler than designing combinatorial logic. In syncronous logic we can arrange the timing so that the next flip-flop downstream never has a clock edge arrive during the time when the upstream logic might glitch, so the glitch never propagates through to be seen at the final outputs of the system.

  • \$\begingroup\$ I guess what I mean is......how do we determine a gates initial output value (0 or 1)?....do we just guess? I mean when looking at a TTL logic NOR gate both transistors will be turned OFF which will give a HIGH input. I guess it makes more sense when Looking at the actual TRANSISTOR logic of it \$\endgroup\$ – user3073 Feb 11 '13 at 6:16
  • \$\begingroup\$ The intial output value depends on the initial input values, just like it does at any other point in time. \$\endgroup\$ – The Photon Feb 11 '13 at 6:43

The quick answer: We don't know, and most of the time we don't care.

The long answer: Manufacturers don't try to make the power-on behavior of simple And/Or/Not/Xor/Etc gates predictable. Therefore, this behavior is not documented in any datasheets. You might be able to measure the behavior, but you cannot say that "This AND-Gate does X, therefore all AND-Gates does X." Different gates will behave differently. It is even possible that the same gate behaves differently on different power-ups.

But let's consider the startup sequence. Let's assume that the chip is rated for VCC=3.3v +/- 10%. So below 3.0v, the behavior of the chip is undefined. But the chip has some extra margin on the voltage, so it will likely operate at +2.9v. So how long does it take VCC to go from 2.9v to 3.0v on power up? It will vary from system to system, but it is likely longer than the propagation delay of the gate itself. What does this mean? It means that by the time VCC gets to within the proper operating range then the gate has come up and the output already reflects the current state of the inputs.

The only time that we actually care is when an output needs to be glitch free at power-up. This is very difficult to guarantee normally. Typically you would have to design some dedicated logic to guarantee this behavior. In audio we do something similar to prevent pops on the audio outputs when power is turned on-- and we do it with relays to keep the outputs disconnected (and pulled to GND) until power is up and stable.

  • \$\begingroup\$ It makes more sense when looking at TTL logic like actual transistor gate logic....Since one Transistor may power on earlier than the other then god knows what happens? makes sense though. \$\endgroup\$ – user3073 Feb 11 '13 at 6:17

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