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I keep hearing CISC architectures consume more power than RISC architectures. This is said to be the reason for using RISC architectures for low-power applications. I am a skeptic, I think it could be possible that the low-power consumption of RISC is just a confirmation bias after seeing examples of low-power RISC architectures.

I am not sure if there is a scientific basis to this. The reason could also be the availability / low-cost of licensing of RISC architectures for embedded applications. The reason that is usually given for RISC consuming lesser power is said to be a lesser complex decoder unit compared to CISC.

Is this true? Do RISC architectures consume lesser power than CISC architectures? Or does CISC vs. RISC really not matter for power consumption?

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    \$\begingroup\$ RISC vs CISC hasn't been relevant in 20 years, so either you're reading something ancient or just nonsense. \$\endgroup\$ Jul 25 at 16:21
  • \$\begingroup\$ Oh, to think people would close this as "opinion-based" when someone has already published a research paper in an IEEE conference on this very topic. \$\endgroup\$ Jul 25 at 17:03
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    \$\begingroup\$ @user1850479 I totally agree with you. But the myth that RISC is low-power when compared to CISC is very prevalent today, especially when you consider it in the light of Apple and Amazon moving to ARM from x86 \$\endgroup\$ Jul 25 at 17:14
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    \$\begingroup\$ It's opinion-based because you're just asking this out of idle curiosity, there's no problem to solve here. An answer will contain no information (=used to make a decision), just trivia. \$\endgroup\$
    – pipe
    Jul 25 at 17:42
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    \$\begingroup\$ The fact that someone published a paper somewhere else on this topic is completely irrelevant to the question of whether it is an appropriate question for this site. \$\endgroup\$ Jul 25 at 18:38
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On the basis you can't link duplication across SE board, I'll duplicate here: https://stackoverflow.com/questions/20298991/does-generally-risc-processors-have-lower-power-consumption-than-cisc-processors

No, they don't.

It was commonly believed in the past that RISC CPUs were more power friendly, mostly due to the large overhead of maintaining the large ROMs needed for CISC. However, a recent study comparing several workloads on multiple platforms finally ended that myth, stating:

there is nothing fundamentally more energy efficient in one ISA class or the other.

It's still true that many implementations of these ISAs are directed at certain market segments that still reflect this classification, you'll find more x86 at the segments with higher power envelopes such as PCs and servers, and more ARM at the low power and embedded segments, but these are mostly design points and marketing decisions. There's nothing fundamental preventing a CISC ISA from entering lower power domains.

Don't mix that with backward compatibility - x86 for e.g. would have a hard time reducing power while still keeping all legacy modes and specialized ISA, but it's another issue. It's also not a real block, as can be seen in Atom based implementations, some of which even going below 1W TDP

Credit to Leeor for linking the study.

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