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I'm implementing this circuit with IC BQ24308 so I need to pick a PMOS for the circuit shown: enter image description here

This is the block diagram of the IC: enter image description here

Design guide picks Si2343DS PMOS as the Qext but I don't understand why as it doesn't explain much about it.

Could you please help me out? Thanks!!

Edit:

Datasheet: https://datasheet.ciiva.com/4873/slus977a-128613-4873872.pdf Design guide: https://www.ti.com/lit/ug/sluu291b/sluu291b.pdf?ts=1627297615026&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FBQ24308

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  • \$\begingroup\$ You should provide a link to the "design guide" and to the manufacturer's datasheet for the bq2430x. \$\endgroup\$ Jul 26, 2021 at 15:05
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    \$\begingroup\$ You can only pick a FET once you know the current, voltage and switching frequency requirements. We can't help you either unless you give us that info. \$\endgroup\$ Jul 26, 2021 at 15:05
  • \$\begingroup\$ @ElliotAlderson thanks I've added the links on the main post \$\endgroup\$
    – EfraAV
    Jul 26, 2021 at 15:18
  • \$\begingroup\$ @JonathanS. my idea is to use it as a protection IC for a battery charger so the input would be 5V DC and the current 1A. About the switching frequency requirements none because it'd be DC voltage, is that right? Thanks!! \$\endgroup\$
    – EfraAV
    Jul 26, 2021 at 15:20

1 Answer 1

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The Ext FET was chosen over the wide input ranges it supports. Like Vds=30, Vgs >17V and power /temp rise for I^2R at low Vin. You can certainly relax Vin and Vgs max. Ron affects local heat rise is your TBD spec. Vgs(th) max needs to guarantee this with 4.5V for say 200 mW at max current ( worst case)

If Vin exceeds Zener clamp, the source is pulled up by a Zener to clamp Vgs on Pgate out. If Vin is less than the zener Nfet pulls the Pfet gate to 0V. I assume this for 15V so 17V gives margin for ext FET Vgs max.

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  • \$\begingroup\$ thanks for replying, what do you mean by "you can relax Vin and Vgs max"? I didn't get that. Also, would Vin=5V turn on the PMOS? I don't understand that \$\endgroup\$
    – EfraAV
    Jul 26, 2021 at 15:55
  • \$\begingroup\$ You don’t need such a wide voltage tolerance 30 vs 5V, with 5V +/- 10% in , 0V turns on Pch so a logic level input FET is needed. Tons to choose from. \$\endgroup\$ Jul 26, 2021 at 15:59
  • \$\begingroup\$ the device would be powered by USB so it'd have 5V that's why I'm asking \$\endgroup\$
    – EfraAV
    Jul 26, 2021 at 16:02
  • \$\begingroup\$ Thats what I answered assuming. But normally you define all these specs before you choose parts and put these specs in the question. \$\endgroup\$ Jul 26, 2021 at 16:04
  • \$\begingroup\$ yes, sorry to keep this going but I still don't understand. What I don't get is what is going on with the external MOSFET and the pin gate. I understand that with PMOS, the gate voltage relative to drain voltage needs to be <0 in order to be activated (right?) But when the Vgclmp gets in , I get lost. What happens if Vin<17V with the Vgclmp? \$\endgroup\$
    – EfraAV
    Jul 26, 2021 at 17:04

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