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I just got a PCB in I designed from fab, and I quickly discovered I made a mistake in the design. I'm using a P-channel MOSFET, D2PAK, as a high-side switch.

Its pinout is (1) gate, (2) drain, (3) source, but I laid it out as if it was (1) gate, (2) source, (3) drain. As it stands, the fully assembled PCBs conduct whether the gate is driven or not via the body diode.

What can I do?

I don't see any MOSFETs with the pinout that I used, so I don't see a way to replace the component to fix the problem. I also don't see a good way to reorient the package in a way that would make for a clean install and a sale-able product.

Any ideas?

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    \$\begingroup\$ Glue it upside down and solder with wires. \$\endgroup\$
    – Eugene Sh.
    Jul 26 at 19:01
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    \$\begingroup\$ Life lesson! No detail is too small! For testing purposes to prove there are no other mistakes, do as Eugene says. \$\endgroup\$ Jul 26 at 19:37
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    \$\begingroup\$ 1. Prototypes aren't meant for sale. 2. You prototype because humans are fallible. 3. Typical prototype quantities are say 2-4 boards (if the boards go into equipment at qty 1). Keeping 2-4 populated ones for your own use in the lab, even if they are not pretty, is normal. You'll almost never go from first layout to market, unless it's just a revision or a simple modification of previous design that doesn't add new (non-library) parts. \$\endgroup\$ Jul 27 at 6:16
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It's unfortunate, but you probably just need to get new PCBs made. You've learned an important lesson today, to always double check your package pinouts!

For the purposes of running tests, you may be able to just cut the traces on the PCB and use wires to connect the FET to what it should be connected to, or connect it with wires while it's insulated from the board, but doing either of these in production is a bad idea.


The reason you can't find any FETs with the pinout you want is a practical one: due to the way VDMOSFETs (a category that includes almost all currently produced discrete MOSFETs) work, the source and gate are on the top of the silicon wafer and the drain is on the bottom. In a D²PAK (as well as many other common packages), the bottom of the die is attached directly to the leadframe's tab, since (among other reasons) this provides good thermal contact between the die and the package (and any heatsink the package is attached to). So pin 2 (the tab) of a FET in a D²PAK package will nearly always be the drain.

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Just 'blue wire' the FET in. You can deadbug the part (turn it upside down) and either bend the pins (very carefully as they are easy to break) or wire a large gauge wire to the pins. (there are some assembly houses that might do this for you also if you create clear instructions). The gate carries almost no current so you can use a smaller wire for that (keep the wire short as it ads inductance if this is a switching application).

If the part doesn't need to dissipate a lot of power, you might be able to get a similar part in a different package (like a TO220) where it might be easier to bend and solder pins.

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    \$\begingroup\$ It's interesting how each group of people has a different colour for patch wire. We call them green wires but they are actually bright orange for inspection \$\endgroup\$ Jul 27 at 7:58
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Consider designing a little daughterboard on which you could put your PMOS.

This will add a production step, but it can be somewhat automated, since the PMOS can be soldered during a normal run on the panelized daugherboards.

Then you would have to separate the daughterboards an plug them on the main boards using some kind of connector. That's better that fiddle with wires, which requires much more workmanship.

If you have little space, you could transfer some of the component near the PMOS from the mainboard to the daughterboard.

Maybe the daughterboard may be built with castellations at board edges and can then be soldered (like this) on the mainboard at a later stage that can be automated.

Of course you should perform a cost/benefit analysis to see if it is more convenient to do this or scrap the old boards and correct the PCB layout of the original board.

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    \$\begingroup\$ I disagree. Daughterboards work for such applications if the system was designed for them from the start. Otherwise, they are a pain and kill performance and reliability. The hassle from rejects and field failures may well quickly eclipse any savings from tossing a small board run out. The only thing I can think of that would work well would be a thin castellated substrate with a smaller part mounted on it (e.g. a power BGA or similar leadless package instead of a leaded one). Some effort for a jellybean part... And I wouldn't trust it without a thermomechanical finite element analysis anyway. \$\endgroup\$ Jul 27 at 6:20
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    \$\begingroup\$ @Kubahasn'tforgottenMonica It depends on economics. If you have 10k boards of consumer electronics stuff and you have enough space around the PMOS, you might be ending with a cheaper solution and not that unreliable. Ofc. it wouldn't be as robust as a new board against vibrations. However there are connectors for boards that are suitable for vibration-prone environment, like press-fit connectors, that are also used for automotive applications. But the point is mainly economical. If the OP had not a cost problem, he would have already scrapped the whole lot of boards. \$\endgroup\$ Jul 27 at 9:40
  • \$\begingroup\$ @Kubahasn'tforgottenMonica Moreover, reliability is always relative to the application and to the planned service life of the product. And labor costs to implement other solutions may be much higher, depending on where the board is assembled or reworked. \$\endgroup\$ Jul 27 at 9:43
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    \$\begingroup\$ @Kubahasn'tforgottenMonica BTW, you seem to be talking from the perspective of high reliability, small(ish) run products, such as critical application control boards, medical instrumentation, measurement instruments or automotive. With low(ish)-cost high volume consumer electronics I doubt anyone performs a FEM analysis of the board (unless this has become very cheap today; I admit I'm not up-to-date on the subject). We don't know anything about the OP application, so any possible solution may be a good candidate for solving the OP problem. \$\endgroup\$ Jul 27 at 9:48

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