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I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's similar to how any standard SPI or I²C interface works - send some instructions to the device, then read back some results until a particular pin state is met. Except in this case the data and address buses are parallel instead of serial.

I have three related questions on the topic:

  • What interface does standard PC memory, e.g. SDRAM or DDR, run on? I remember reading something about JEDEC being responsible for the spec, but I can't find any specific details. I'd like to use DDR (or DDR2) since it's cheaper right now, but I'll settle for SDRAM.
  • Can standard PC memory be bought down to more "comfortable" clock speeds? The standard bus speeds for these things tend to be around 133MHz, but I'm hoping to run them at less than 1MHz. My understanding is that SDRAM wait for clock edges before responding to commands, so a low clock frequency should result in it being manageable by a microcontroller.
  • What's the name of the physical interface? I tried looking on Farnell for sockets for such memory devices, but I only found some really tiny pitch surface-mount stuff. I could probably build my own through-hole version if I spent long enough, but I'd prefer to just buy one pre-built.
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  • \$\begingroup\$ Given the large number of connectors, you're not going to find it in through-hole. You may hit problems with DRAM refresh: each bit needs to be rewritten at a particular minimum frequency if it is not to be lost. You might be best off finding an ARM with a DRAM interface .. \$\endgroup\$ – pjc50 Feb 11 '13 at 15:12
  • \$\begingroup\$ Go to Micron.com and look for their excellent datasheets and technical notes. The DIMM datasheets give some information, but the real meat is in the datasheets for the chips fitted to those DIMMs. \$\endgroup\$ – Brian Drummond Feb 11 '13 at 15:14
  • \$\begingroup\$ What kind of mcu are you using that will give you 100+ gpio for the data, address, parity, and control pins needed for SDram? \$\endgroup\$ – Passerby Feb 11 '13 at 21:36
  • \$\begingroup\$ @Passerby I was hoping to reduce the necessary pin counts by feeding the address and data buses with shift registers. Looks like a micro won't be quick enough, though. \$\endgroup\$ – Polynomial Feb 11 '13 at 22:47
  • \$\begingroup\$ @Polynomial well, what is your memory needs? You could salvage a single ram chip off a dimm instead. Especially older memory (before sdram pc100). Still get a meg or two, from a single memory chip. \$\endgroup\$ – Passerby Feb 12 '13 at 0:42
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Unless your microcontroller has a direct bus support for interfacing to DDR/DDR2/DDR3 type RAM or your microcontroller is interfaced through an FPGA which has been programmmed to provide the RAM interface then it is likely that futzing around with DIMMs is not a useful exercise. There are several strong reasons why this is the case....

1) DDR memory chips may be operating at lower voltages than your microcontroller.

2) The interface to the DDR memory is multiplexed and requires precise clocking whilst the multiplexed lines change states in sync with said clock.

3) Modern DIMMs are designed to operate at very high frequency clocks of 800MHz, 1066MHz, 1333MHz, or 1600MHz. Signal integrity is extremely extremely important when designing the circuit connections to the DIMM. It is not a trivial exercise and the memory chips can be extremely sensitive to noise as a result.

4) DDR memories require constant refresh to keep the memory cells data valid. Without refresh the memory content fades away over time from milliseconds to seconds.

5) The command structure to operate modern DDR RAMs is complex. The most complicated part is getting the initialization sequence correct which consists of some 13 to 20 individual steps.

6) Modern DIMMs are designed to feed data to modern PC type computers very fast. The typical DIMM has a data path width of 64-bits. Multi rank DIMMs also require multiple clocks and chip select signals to access all of the memory chips on the memory stick. It is unlikely that the typical small microcontroller can make effective use of this wide data format without an excessive amount of external circuitry.

Keep this in mind too. Companies that make PC style processors that utilize DIMMs have onboard controllers to interface to the memory sockets. There is an engineering specialty for programmers that work in the BIOS field called MRC (memory reference code). This is the program code module that initializes the DDR controller and all the attached DIMMs. This specialty employs the best and some of the most senior BIOS programmers that do nothing but MRC coding as a full time job.

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Some single data rate (SDR) SDRAM can be run at slower rates - check the Clock Period (max) spec. However, you have to issues refresh commands on a regular basis, and if you clock at 1MHz you might find you have no time for anything else!

DDR SDRAM typically has a minimum (yes, minimum) clock frequency in the high tens of MHz... and the physical interface would be very challenging to implement on a micro as it returns a clock/strobe-like signal along with the data and you have to find the middle of that clock period to know when to sample the data.

Micron is a great source for datasheets which document the interfaces very well.

As for physical connectors, they are called SIMM and DIMM (single and dual inline memory module)

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  • \$\begingroup\$ This is first sane answer to a question about DDR and MCUs I read here. DDR has minimum clock frequency, damn! That's constraint which precludes usage with low-freq MCUs, not trivialities like pin count or Vcc (ATtiny can do 1.8V). As for refresh, I wish that some of pro guys described why "auto refresh" typically found in DDR datasheets won't work here (or why "auto refresh" isn't really auto refresh). \$\endgroup\$ – pfalcon Jun 9 '13 at 1:26
  • \$\begingroup\$ Wouldn't minimum clock period be maximum clock frequency? I also bumped into this micron.com/~/media/Documents/Products/Technical%20Note/DRAM/… which says "Unlike DDR, there is no minimum clock frequency for SDRAM regardless of the speed grade." That document made it sound like you only need to look at the refresh related parameters. \$\endgroup\$ – Aleksi Torhamo May 29 '14 at 0:00
  • \$\begingroup\$ Yes, the basic circuit still consists of a capacitor. If it has a charge, it's "1" otherwise it's "0". The charge on a capacitor decays over time, and the capacitors are small. The circuitry and timing to "refresh" the charge is an overhead. \$\endgroup\$ – Alan Campbell Nov 8 '14 at 23:25
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In order to use SDRAM, you need to have a chip that contains an SDRAM controller, period. Either get a microcontroller that has one, or attach an FPGA that has one to your microcontroller.

Either way, it isn't a project for a beginner.

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