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A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE involves the speed at which VLSI process development (circuit complexity, design rules, speed) might happen in silicon carbide compared to silicon.

There's an argument that SiC will remain 50 years behind silicon, I've argued that with all the advanced manufacturing toolsets, device and circuit modeling software already in place process shrink could happen far faster for a new material than it did for silicon historically.

I'd mentioned these ring oscillator test structures from 2016 Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions (from this answer) and have since found the 2019 paper Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications (also here)

Question: What is the current state of the art design rule for SiC VLSI? What are the technological impediments to shrinking to a design rule sufficiently to start making modern micro-controllers and low speed image processors on SiC for a spacecraft to land on Venus and operate at ~460 °C?

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    \$\begingroup\$ Maybe carbon nanotube uC are 50 yrs behind SiC \$\endgroup\$ Jul 27, 2021 at 1:18
  • \$\begingroup\$ Venus might not be your target market, even though it is an interesting application , if it was viable or reliable it would be down the drilling holes and other terrestrial 200-400C environments, instead they rely on passive and analog sending devices or short lifetimes e.g. 5hours and then dissolved with acid. \$\endgroup\$
    – crasic
    Jul 27, 2021 at 1:22
  • \$\begingroup\$ Did you ask crystec? \$\endgroup\$ Jul 27, 2021 at 1:24
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    \$\begingroup\$ Is it necessary that the electronics work just at 460°C or that they work in the range of temperatures from -70 to 460°C ? The latter would be even more difficult I think. \$\endgroup\$
    – AJN
    Jul 27, 2021 at 1:39
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    \$\begingroup\$ @AJN yes that's certainly an issue due to thermal ionization of dopants. For the purposes of this question let's assume it can tolerate those swings during storage, but have a nominal operating range of say 460 +/- 50 °C \$\endgroup\$
    – uhoh
    Jul 27, 2021 at 1:44

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Right now, there are two major (published) efforts developing IC processes for long-term Venus landers:

The current state-of-the-art layout rules for the NASA process are published on NASA's website here. The process has 3 µm N-channel JFETs, resistors, and 2 layers of metal. While I don't think the KTH process rules are published, your linked paper does have dimensions for the NPN transistors in their process. If you lower the long-term reliability temperature to say 350C, then MOSFETS have been demonstrated as short as 1.2µm.

Right now, there are a few problems slowing down the adoption of silicon technology advances:

  • Lack of a high-temperature, long-term survivable gate oxide for (C)MOS devices. Long-term reliable parts use oxide-free devices (JFET, NPN).
  • Implant difficulties requiring different implanters
  • Lack of investment (compared to 1970's microelectronics)

Most of the materials in SiC processing are similar to those used in silicon, but they're almost all different. That means that almost everything requires process development. The power SiC developments are focusing on minimizing cost and maximizing performance (at <200C), so the biggest market driver of SiC technology is really only improving the base wafers (which are currently 6" and looking to move to 8").

I think the premise you have in your question:

"There's an argument that SiC will remain 50 years behind silicon, I've argued that with all the advanced manufacturing toolsets, device and circuit modeling software already in place process shrink could happen far faster for a new material than it did for silicon historically."

is fundamentally correct, but the number of people chipping away at the problem is much fewer than people developing ICs in the 70's. The benefits mean that with such an investment, most of the work is focused on process development instead of inventing/improving lithography, modelling, packaging, etc. from scratch.

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