Assuming we are using NOR gates to build the RS flip flop.
After reading so much material on RS flip and flop circuit, I understand that:
When S=1, R=0, Q=1, and Q̅=0, for the next clock cycle, Q'=1 (Q' means the output of Q at next clock cycle, and I see Q' is used for that purpose in some textbooks)
But when S=1, R=0, Q=0, and Q̅=1, OBVIOUSLY both NOR gates have input 1, so that both outputs Q' and Q̅' are 0, and this is illegal.
In more detail:
S=1 and Q=0 will cause the bottom gate to output 0, that is Q̅'=0 (essentially, the bottom gate has input of 1).
R=0 and Q̅=1 will cause the top gate to output 0, that is Q'=0 (Essentially, the top gate has input of 1).
So in summary S=1, R=0, Q=0, Q̅=1 have the same effects as S=1 and R=1 (S=1 and R=1 is INVALID input).
Picture at the bottom shows the circuit.
I see in many materials that they list S=1, R=0, Q=0, Q̅=1 as a VALID input, but essential I think it is also invalid since such a combination is the same as S=1 and R=1.
Can you point out what is wrong with my understanding?
@Carl I added a new picture as below with a more complete truth table compared with the one proposed by you.
I added a picture from the textbook for ALevel computer science. You can tell that line underlined in red color, according to this book:
S=1 and Q=0 results in Q̅ (under final state, denoted as Q' in this picture) = 0.
R=0 and Q̅（under initial state, denoted as Q' in this book）= 1 results in Q=1 (under final state).
R=0 and Q̅（under initial state, denoted as Q' in this book）= 1 results in Q=0 (under final state)
Anything wrong with my understanding?
To my knowledge, both Q and Q̅ will give feedback, so each time the top gate has two inputs from R and Q̅, and the bottom gate has two inputs from S and Q. Please correct me if any misunderstanding.