# For an RS flip-flop, what if S = 1, R = 0, Q = 0, and Q̅ = 1? Is it legal or not? Why?

Assuming we are using NOR gates to build the RS flip flop.

After reading so much material on RS flip and flop circuit, I understand that:

When S=1, R=0, Q=1, and Q̅=0, for the next clock cycle, Q'=1 (Q' means the output of Q at next clock cycle, and I see Q' is used for that purpose in some textbooks)

But when S=1, R=0, Q=0, and Q̅=1, OBVIOUSLY both NOR gates have input 1, so that both outputs Q' and Q̅' are 0, and this is illegal.

In more detail:

S=1 and Q=0 will cause the bottom gate to output 0, that is Q̅'=0 (essentially, the bottom gate has input of 1).

R=0 and Q̅=1 will cause the top gate to output 0, that is Q'=0 (Essentially, the top gate has input of 1).

So in summary S=1, R=0, Q=0, Q̅=1 have the same effects as S=1 and R=1 (S=1 and R=1 is INVALID input).

Picture at the bottom shows the circuit.

I see in many materials that they list S=1, R=0, Q=0, Q̅=1 as a VALID input, but essential I think it is also invalid since such a combination is the same as S=1 and R=1.

Can you point out what is wrong with my understanding?

@Carl I added a new picture as below with a more complete truth table compared with the one proposed by you.

I added a picture from the textbook for ALevel computer science. You can tell that line underlined in red color, according to this book:

S=1 and Q=0 results in Q̅ (under final state, denoted as Q' in this picture) = 0.

R=0 and Q̅（under initial state, denoted as Q' in this book）= 1 results in Q=1 (under final state).

But OBVIOUSLY:

R=0 and Q̅（under initial state, denoted as Q' in this book）= 1 results in Q=0 (under final state)

Anything wrong with my understanding?

To my knowledge, both Q and Q̅ will give feedback, so each time the top gate has two inputs from R and Q̅, and the bottom gate has two inputs from S and Q. Please correct me if any misunderstanding.

• This circuit doesn't have a clock. There are no clock cycles. You seem to misunderstand something. Jul 27, 2021 at 11:20
• Does this answer your question? Why is S=1, R=1 state forbidden in RS flip flop? Jul 27, 2021 at 11:26
• ¬Q is an output, not an input. If S is high and R is low, then Q must be high and ¬Q must be low. If you force ¬Q high, you're driving an output, which is not permitted. Jul 28, 2021 at 3:28
• @ElliotAlderson thanks for reply. But as I mentioned in the question, I know S=1 and R=1 is a wrong input for sure. My question is S=1, R=0, Q=0 and Q bar=1 would result the same input as S=1 and R=1, so S=1, R=0. Q=0 and Q bar =1 is also INVALID. But all books say it is right. What is wrong with my understanding? Aug 2, 2021 at 9:38
• By definition, Q and Q bar are outputs. They are not used as inputs. Ever. Aug 2, 2021 at 10:47

Yes, your understanding is flawed. Especially this quote shows it

however, I see in many materials, they list S=1, R=1, Q=0, Q bar=1 as valid input.

Instead of picking out all your misunderstandings, perhaps it's best to show you the actual behavior of the SR-latch with a function table.

$$\begin{array}{rl} \begin{smallmatrix}\begin{array}{rr|ccc} S & R & Q & \overline{Q} & \text{comments} \\ \hline 1 & 0 & 1 & 0 & \\ 0 & 0 & 1 & 0 & \: \: \text{after S = 1, R = 0}\\ 0 & 1 & 0 & 1 & \\ 0 & 0 & 0 & 1 & \: \: \text{after S = 0, R = 1}\\ 1 & 1 & 0 & 0 & \: \: \text{forbidden} \end{array}\end{smallmatrix} \end{array}$$

When $$\(S,R)=(1,0) \Rightarrow Q=1\$$ no matter what state came before it. The output is set.

When $$\(S,R)=(0,1) \Rightarrow Q=0\$$ no matter what state came before it. The output is reset.

When $$\(S,R)=(0,0)\$$ the output latches on to its previous state and doesn't change.

The outputs $$\Q\$$ and $$\\overline{Q}\$$ are normally the complement of each other. However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 occurs. If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable state (metastable state). Consequently, in practice, setting both inputs to 1 is forbidden.

• S=1,R=1 is actually fine (both outputs 0), the problem occurs after setting S=0,R=0 again Jul 27, 2021 at 11:20
• @user253751 You are right, I will make an edit.
– Carl
Jul 27, 2021 at 11:22
• It's not even necessarily a problem if S and R become 0 at different times. Jul 27, 2021 at 11:23
• @user253751 I disagree with saying that S=R=1 is "fine". The latch outputs will be incorrect in that case, and you do not know what that will cause subsequent logic to do. This incorrect output state could cause undesirable behavior somewhere else in the system. Jul 27, 2021 at 11:23
• @ElliotAlderson well it's certainly not metastable, and it's well-defined behaviour of the latch. Perhaps it's forbidden in the context of your system, but there are surely many other invalid states your system forbids, and we don't attribute them all to the individual components of the system. Jul 27, 2021 at 11:31

The easiest way of thinking about this is simple. Imagine you have a motor running a pump. You have two buttons: start and stop. When you press the start, the motor starts. Then you don't have to stand there and hold the button in any longer. When you press the stop button, it stops. You don't need to hold the button down any longer.

Start button is like S=1. You aren't pressing the Stop button, so R=0. Motor runs. Q=1.

Pressing the stop button and not touching the start button is like S=0 and R=1. Motor stops. Q=0.

Not pressing either is S=0 and R=0. This is a sensible state, because it only means you aren't pressing either. You don't want to stand there all day holding a button down, do you? Whatever button you pressed earlier will be remembered, because that is the point of this circuit. To remember which button you pressed last. Q=whatever button you pressed last.

Pressing both S and R at the same time is like pressing the start and stop button at the same time. Various books will call this "illegal", "forbidden" "not-allowed". Why would you tell a motor to start and stop at the same time? There is no sense in analyzing this condition because you would never tell a motor to start and stop at the same time.

It is pretty simple when you look at it this way.

It's more a philosophical than a practical issue.

In fact some people say it's only a latch since it's asynchronous.

The input is considered legal only if the latch state becomes legal.

Since the outputs are declared to be one the inverse of the other, asserting both inputs is considered illegal since the outputs become equal.

However if you only use one of the outputs it become legal and useful since now you have one priority input: just dont call it a S/R latch.

The other important reason is that this allow to better explain the transition and the motivation to the J-K flipflop.

Your question (since updating it to R=0, S=1, Q=0, /Q=1) is perfectly valid.

What you must realize is

• You have an SR latch, not a flip-flop. There is no clock; thus it is an error to say anything about "for the next clock cycle".

• The conditions you have stated are transient and will only exist dynamically.

In particular, your described combination arises in the following scenario:

• The latch has been holding 0 (R=0, S=0, Q=0, /Q=1). This is a valid and stable state.

• A rising edge arrives on input S.

The NOR gates will have some "propagation delay" before a change at the input produces a change at the output.

The NOR gate driving Q is initially consistent. Q = R NOR /Q, with R=0 and /Q=1 gives Q=0 as before. The NOR gate driving /Q is made inconsistent by the edge on S. /Q = S NOR Q, with Q=0 and S=1 produces a falling edge on /Q.

Now, just momentarily, the combination R=0, S=1, Q=0, /Q=0 may be observed. But this falling edge on /Q makes the NOR gate driving Q inconsistent, leading to a rising edge on Q.

Thus you can observe the following sequence

1. R=0, S=0, Q=0, /Q=1

2. R=0, S=1, Q=0, /Q=1

3. R=0, S=1, Q=0, /Q=0

4. R=0, S=1, Q=1, /Q=0

but the two intermediate states are transient and last one propagation delay each, typically just a couple nanoseconds for reasonably modern discrete NOR gates, or a fraction of a nanosecond for NOR gates integrated into a larger IC (due to the fact that internal connections have much lower capacitance than I/O pins).

The transient states are so fast you can't see them unless you are using a GHz scope or logic analyzer, and the probe characteristics may easily affect the observed rise and fall times or even order of events. But if you had further logic combining two or more of these signals, you might get glitches that unexpectedly activate edge-detector logic, so it also isn't a great idea to pretend that intermediate states never happened.

When S=1, R=0, Q=0, and Qbar=1, then both NOR gates have an input set to 1, so both NOR gates output 0 - you are correct so far. But as soon as that happens, now only one NOR gate has an input set to 1, and now the output becomes Q=1 and Qbar=0 and stays there.

What you have discovered is that logic circuits take time to update their outputs and until the outputs settle on the correct new values, they could temporarily have invalid values. For example, an OR gate could output 0 for a brief moment when input A goes from 1 to 0, even if input B is still 1. This is called a "glitch".

This must be taken into account when designing logic circuits. If your logic circuit has no memory, then internal glitches can only cause output glitches, and the output will be correct after a brief moment, which is usually okay. If your circuit has memory and a clock, you make sure the clock is slow enough that all glitches go away before the next clock pulse comes. That way, there is no chance that a glitch accidentally gets stored into a memory unit. If your circuit has memory and no clock, this can be a very serious and difficult problem, because glitches can accidentally get stored in memory units and then they don't go away after a moment. So you must be extremely careful when designing such circuits, and in fact, it is recommended to simply use a clock so that you don't have to deal with the problem.

"Legal" or "not" ?

I belong to an old school and the tables of behavior of the RS flip-flops (modern ?) sometimes seems to me "little" explanatory and not very understandable (sometimes "false").

I propose, as for me, to explain the operation of a FF-RS ​​(carried out with NAND) by simple means. Adaptable for "any" other FF or sequential circuit.

Important note : outputs are labelled (Q1 Q2) (general) and not Q and \Q !

See the "modified" figure. And the result of the (Q1 Q2) outputs accordingly.

This FF can be "broken down" into a combinatorial circuit with now 4 inputs (2 inputs R, S, and 2 other inputs _q1, _q2 or more simply q1, q2 which are the cut return of Q1 and Q2).

We can therefore fill a Karnaugh table with 4 variables (q1 q2 R S) with the outputs (Q1 Q2).

I use the simulator to help full filling the k-map. U1 is the generator of the 16th "inputs" states.

We can see the corresponding results of (Q1 Q2) without efforts.

Let us than fill the K-map. It is easy when the "variables" are in the "right order".

In this table, we therefore see boxes where the combination of (q1 q2) is the same (in the same order!) as (Q1 Q2).

These states are therefore stable "combinations". The other boxes are therefore unstable.

This therefore makes it possible to follow the real evolution of a sequential circuit.

Example of use : Let (R S) = (0 0) ( first column, first line -> (q1 q2) = (0 0) ).

We see that, whatever are (q1 q2), the destination line is the 3th in the table

where (Q1 Q2) = (q1 q2) = (11) which is STABLE.

But we have not Q1 = Q and Q2 = \Q (\Q = complement of Q) !

But if we do not use the combination (R S)= (0 0), this is not important, but permitted anyway and "usable" if necessary. Not "usable" as (Q \Q), but not "forbidden" as (Q1 Q2).

Can you follow (slowly) the behavior of the outputs (Q3 Q4) ?

And now, can you apply this to the RS-FF with NOR gates ?

Here, starting with (R1,S1)=(0,0) and initial conditions (Q3,Q4)=(1,1).

All delays of 23 ns. Do you see the starting oscillation (when (R,S) =(0,0)) between first and third line (K-map)?

Here "random" delays