I want to sniff some data from a SPI Bus between boards from a loom machine. The bus starts at J9 from PCB 5722 and goes through 8 boards named PCB 5778, which I guess are the slaves. The connector where the BUS starts has 14 pins and some of them are /OUTEN_EXP, SI, CKOUT+, CKOUT-, CEOUT+ and CEOUT-. The BUS goes through connectors J3 and J4 of each 5778 board and comes back to PCB 5722 on connector J10 which seems to have 2 termination resistor between CKOUT+ and CKOUT- and CEOUT+ and CEOUT-
I guess those are the corresponding pins in a single-ended spi line
(4 at the start) SI -> MOSI
(6 & 8) CKOUT -> CLK
(10 & 12) CEOUT -> CE / CS / SS
(4 at the end) SO_MID -> MISO
Is that normal for SPI to have CKOUT+ and CKOUT- and CEOUT+ and CEOUT-? Looks like differential pairs. After some research I found that in some cases LVDS can be used on SPI to increase the length of the bus. Is that the case?
Also, the lack of more CE pins leads me to think it's connected in a Daisy-Chain topology.
Any tips on how can I sniff the data from this BUS?
Edit:
I took some measurements with a scope right before J10 at the end of the line, here they are:
1 - CEOUT+ && CEOUT- with reference to GND
2 - CKOUT+ && CKOUT- with reference to GND
3 - Delay between CEOUT going low and CKOUT starting (3us)
4 - CKOUT stays on during 385us, considering it is 1 Mhz, it means the message has 385 bits = 48 bytes, right?
5 - SI signal stays HIGH when CEOUT is inactive, does that means something?
6 - Measuring SI and CKOUT+ is possible to conclude it reads the bits at rising edge, right?
With that in mind
Can you identify what standard is that? (RS485, LVDS, TTL...)
What receiver would you recommend to read these signal?
Is that a way for me to simply connect in parallel and drop the voltage of the CKOUT+ and CEOUT+ in 1V to identify when it is HIGH and LOW and connect directly to a microcontroller pin and read it like a normal SPI?