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I want to sniff some data from a SPI Bus between boards from a loom machine. The bus starts at J9 from PCB 5722 and goes through 8 boards named PCB 5778, which I guess are the slaves. The connector where the BUS starts has 14 pins and some of them are /OUTEN_EXP, SI, CKOUT+, CKOUT-, CEOUT+ and CEOUT-. The BUS goes through connectors J3 and J4 of each 5778 board and comes back to PCB 5722 on connector J10 which seems to have 2 termination resistor between CKOUT+ and CKOUT- and CEOUT+ and CEOUT-

I guess those are the corresponding pins in a single-ended spi line

(4 at the start) SI -> MOSI

(6 & 8) CKOUT -> CLK

(10 & 12) CEOUT -> CE / CS / SS

(4 at the end) SO_MID -> MISO

enter image description here

enter image description here

Is that normal for SPI to have CKOUT+ and CKOUT- and CEOUT+ and CEOUT-? Looks like differential pairs. After some research I found that in some cases LVDS can be used on SPI to increase the length of the bus. Is that the case?

Also, the lack of more CE pins leads me to think it's connected in a Daisy-Chain topology.

Any tips on how can I sniff the data from this BUS?

Edit:

I took some measurements with a scope right before J10 at the end of the line, here they are:

1 - CEOUT+ && CEOUT- with reference to GND enter image description here

2 - CKOUT+ && CKOUT- with reference to GND enter image description here

3 - Delay between CEOUT going low and CKOUT starting (3us)

enter image description here

4 - CKOUT stays on during 385us, considering it is 1 Mhz, it means the message has 385 bits = 48 bytes, right?

enter image description here

5 - SI signal stays HIGH when CEOUT is inactive, does that means something?

enter image description here

6 - Measuring SI and CKOUT+ is possible to conclude it reads the bits at rising edge, right?

enter image description here

With that in mind

Can you identify what standard is that? (RS485, LVDS, TTL...)

What receiver would you recommend to read these signal?

Is that a way for me to simply connect in parallel and drop the voltage of the CKOUT+ and CEOUT+ in 1V to identify when it is HIGH and LOW and connect directly to a microcontroller pin and read it like a normal SPI?

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  • 1
    \$\begingroup\$ Are you sure this is SPI? It doesn't sound much like SPI to me. \$\endgroup\$
    – Hearth
    Jul 28, 2021 at 14:47
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    \$\begingroup\$ Welcome to the site. The SPI bus protocol does not care what signalling standard is used between devices. It's the circuit designer who's to care about that and get it right. The standard per wire can be TTL, LVTTL, LVDS, RS485 or anything else that can carry a single binary level and meet the timing requirements of their particular bus. Using SPI with differential signalling between boards in commonplace and I've worked on systems using it. Anyway: please edit your question to list each of your diff signals with the single-ended SPI signal they represent: SCLK, MOSI, MISO or a chip select. \$\endgroup\$
    – TonyM
    Jul 28, 2021 at 14:54
  • \$\begingroup\$ Are you trying to debug link errors or monitor valid data or ?. Do you know anything about the physical layer signals? \$\endgroup\$
    – Tony Stewart EE75
    Jul 28, 2021 at 15:03
  • \$\begingroup\$ Save yourself a lot of work and get a logic analyzer. Depending on the logic analyzer you use you may have to make a translator for the voltage. \$\endgroup\$
    – Gil
    Jul 28, 2021 at 19:00

1 Answer 1

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I agree with you about SPI for it's resemblance, that has strobe, clock, data out, and data in. It just uses buffers/drivers (PHY) instead of direct logic level signaling. Assuming so:

For CLK & CE, the driver & receiver front ends are "differential", "shunt terminated" at the receiver end of the "master"(pin 6-8 & 10-12). These are likely RS422 or RS485. I would scope it, then attach a 422/485 receiver.

Data line (SI -> SO_MID) is single ended. Possibly, it is pulled-up (open collector/drain, shared, dot-ored). That is to simplify the hardware arbitration while fitting SPI protocols to "ring topology".
Meantime, data line can be shared with other signaling as well, if you see other activities than data on this signal line. Check the signal level, then attach a buffer.

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  • \$\begingroup\$ I edited the question and added some measurements with a scope \$\endgroup\$
    – Diego Ramos
    Jul 30, 2021 at 14:17
  • \$\begingroup\$ @DiegoRamos You are on the right track, and telling that you understand the fundamentals. I'd rather not answer directly and take fun out of your credit. :-) But, just one thing, as you would've decided already; It doesn't matter whether it is 422, 485, LVDS, single-ended, or differential, as long as you can read it out. You just do not want to damage the DUT. Right? \$\endgroup\$
    – jay
    Jul 30, 2021 at 14:39
  • \$\begingroup\$ What "DUT" means? Actually I'm a newbie at stackexchange, it's my first question and I never used it very much \$\endgroup\$
    – Diego Ramos
    Jul 30, 2021 at 16:41
  • \$\begingroup\$ @DiegoRamos Sorry about that jargon. It is "Device Under Test", your loom. I can't stop thinking of getting my hands on it. :) A little explanation about my attitude: StackExchange has rules that I agree with. And, I like the concept of helping people with self-development. I will try to help you, as long as it falls in the StackExchange's philosophy (that I need to learn more), and you need to show your efforts. \$\endgroup\$
    – jay
    Jul 30, 2021 at 16:52
  • \$\begingroup\$ My goal is to read this SPI using an ESP32 \$\endgroup\$
    – Diego Ramos
    Jul 30, 2021 at 18:10

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