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I'm getting some errors when I try to compile my design in Aldec's Active-HDL.

# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (79, 0): There is no default binding for component "buf". (No entity named "buf" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (157, 0): There is no default binding for component "INV". (No entity named "INV" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (277, 0): There is no default binding for component "GND". (No entity named "GND" was found).

I have added these items to the library multiple times, and in different ways, but it still gets hosed up. I'm wondering if anyone else has had a similar issue? I inherited a large design I'm converting from EDIF to VHDL and switching from Virtex-4 to Virtex-5, and there seems to be a symbol resolution problem.

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Could you share your 'library' and 'use' statements in your code. And the lines where those components (buf, INV, GND) are used. My first guess it that you're missing the Xilinx unisim library.

library UNISIM;  
use UNISIM.Vcomponents.all;
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You need to download Xilinx libraries for Active-HDL from www.aldec.com. After downloading, install the library. This will install all the Xilinx library that you need and attach them with Active-HDL.

Also make sure you use proper library and use statement in your code - just like explained in the previous post.

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I ended up contacting support @ Aldec; it ended up being that there was an item in the design that had a mangled global identifier and it caused their parser to choke internally. It was forwarded to the Dev team and they're going to patch it in the next revision.

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