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We are using N-Type Enhancement MOSFET to control power supply to the sensor.

  • MOSFET: AO3400
  • Sensor: ICM-20600

Earlier, we have been using following circuit: enter image description here

With this circuit we didn't have problems in our software. But since both gate control voltage and Vdd on the drain side are 3.3V, it caused high voltage drop on transistor.

Then, we changed the circuit to following: enter image description here

In other words, we just moved the load to the drain side to have higher Vgs.

Now voltage drop on the transistor is very low, but we have problem in the software. Now, we have to add a delay of ~200ms after turning on the transistor, in order to use the sensor (by use I mean read I2C registers). It doesn't work otherwise. Now I want to understand what causes this delay.

Some interesting observations:

  1. When multimeter was connected in voltage measurement mode between ICM GND pin (drain) and GND (source), it was working great. Once disconnected issue started again.
  2. We added capacitor on Vdd side, it fixed problem for some time. But later issue happened again with this configuration.

We are using following circuit for the ICM sensor: enter image description here

Pins 5, 6, 7, 8, 11 and situationally pin 1 (address pin) have GND connections. I have suspicion that it may also cause problems. You see, earlier, since load was on source side, these ground connections were direct. Now, they go trough transistor. When all these pins(1,5,6,7,8,11) are connected to transistor drain side, issue persists.

If someone have any ideas please let me know. I need to fix this delayed behavior.

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    \$\begingroup\$ Post full schematics. Most likely disconnecting ground is a bad idea as many pins could be grounded via MCU so it is powered by leakage via IO pins. \$\endgroup\$
    – Justme
    Jul 29 at 11:46
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    \$\begingroup\$ Please don’t switch ground to ICs. SHDN/EN pin on the IC or high side switch. \$\endgroup\$
    – winny
    Jul 29 at 11:59
  • \$\begingroup\$ Note that various inputs to the ICM chip are probably -ve (wrt its GND pin) when it is off. That ... can't be good. Either fix ALL of those, one by one, or use a PMOS as a high side switch (gate LOW to turn on, either in software or via at inverter) \$\endgroup\$ Jul 29 at 15:39
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Yes, your first circuit is a source follower so it will not be a good choice. Your 2nd circuit will work but, regards the start-up delay this may be the problem...

The data sheet has a clue: -

enter image description here

And that 100 ms assumes the chip is powered prior to being enabled so, it may be even longer from a true cold start.

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  • \$\begingroup\$ Hi, thanks a lot for your answer. I also saw this value on the datasheet. But why then first circuit doesn't cause this delay? \$\endgroup\$
    – UserRR
    Jul 29 at 11:55
  • \$\begingroup\$ @UserRR that could be explained by having one (or more) of the inputs to the chip high and thus powering the device via the input protection diodes. It can happen like this with CMOS devices. \$\endgroup\$
    – Andy aka
    Jul 29 at 12:09
  • \$\begingroup\$ We measured the voltage between Vdd and gnd pin of IC when transistor was off in first circuit, and it was 0V. Do you think it is still possible that it was powered up? \$\endgroup\$
    – UserRR
    Jul 29 at 12:16
  • \$\begingroup\$ @UserRR we could continue this fascinating discussion all day but the problem of the 100 ms timing will exist long after we have both fallen asleep. I can't guess what your full circuit is and, I really don't see any point given what the data sheet tells us. \$\endgroup\$
    – Andy aka
    Jul 29 at 12:19
  • \$\begingroup\$ Alright :) Thank you. \$\endgroup\$
    – UserRR
    Jul 29 at 12:21
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It sounds like reset/brown-out circuit was partially powered through IO pins, with the high-side switching. Try setting all the IO connections to 'low' at power down of the ICM-20600. And, likely, it will go through the reset sequence + delay at turn on.

The intention seems to be power-saving / power-sequencing, right? Generally, chips are not designed to switch Vdd only, while IO-s are active. IO pins have multiple paths to leak power to internal circuitry, especially through the clamping mechanisms. Some of the pins, like power pin, could be directionally coupled to the rail, so do not see the voltage from IO pins. Some devices carry power control pin for that particular purpose, likely isolates all the IO at power down mode.

There are better switching FETs for this purpose, I guess. And, there are devices built for this purpose. I usually do not agree switching ground (low-side) for power control. That can introduce confusion, leakage to other devices, and most importantly "GROUNDing" problem.

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