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Why does NOR flash memory have 0% bad blocks and ECC is not mandatory? From my understanding, NOR flash and NAND flash are made of similar flash cells (they are only "externally" wired in different ways.) Why does NAND memory have a lot of bit errors and need ECC, while NOR flash is handled as a memory type without bit errors?

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    \$\begingroup\$ Why does NOR flash memory has 0% bad blocks That's not the case. ECC is not mandatory Who defines what is mandatory and what not? \$\endgroup\$ Jul 29, 2021 at 12:47
  • \$\begingroup\$ A little more on what Marcus said. Whether or not ECC is needed with any type of memory depends on the application, the type of data being stored, the susceptibility of the memory cell to upsets (errors), and other criteria. You just can't make a broad statement that X-type of memory doesn't need ECC while Y-type of memory does. \$\endgroup\$
    – SteveSh
    Jul 29, 2021 at 12:55
  • \$\begingroup\$ Ok, thanks for the ECC part. But let's consider the bit errors now. On community.cypress.com/t5/Nor-Flash/… there is mentioned by an Infineon employee that "NOR flash has 0 Bit Error Rate and 0 bad block as far as the working condition meet device specification.". How can NOR flash guarantee that all flash cells are fine? The linked page is not the only page mentioning "0% Bad Blocks" for NOR. \$\endgroup\$
    – gott18
    Jul 29, 2021 at 12:58
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    \$\begingroup\$ The flash cells may be similar in concept but rather different in execution. Nand cells are usually much smaller thus getting much better density at the expense of reliability. That’s the price to pay. \$\endgroup\$
    – Kartman
    Jul 29, 2021 at 13:00
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    \$\begingroup\$ @gott18 Nothing in this universe has 0 error rate. Nothing. So, I don't even have to read that: it's marketing. Or worse, it's simply a clueless community moderator, not someone you should trust on physics of semiconductor devices. \$\endgroup\$ Jul 29, 2021 at 13:03

3 Answers 3

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Why does NOR flash memory has 0% bad blocks

This statement is wrong.

and ECC is not mandatory?

That depends on who defines what is mandatory and what not. In general, this statement is not true, either.

For my understanding NOR flash and NAND flash are made of similar flash cells

Well, as the name says, they are different,

(they are only "externally" wired in different ways)

This statement is in this shape wrong. Wikipedia has an article that explains the differences in the cell design at least schematically well:

NOR
NOR flash

NAND
NAND flash

As you can see, in NOR flash the floating gates are spaced less densely; this comes with consequences for the physical semiconductor design. So, these aren't "identical but for the wiring".

So why does NAND memory have a lot of bit errors and needs ECC, while NOR flash is handled as a memory type without bit errors?

This is a bit of generalization: you can build NAND memory that can have much lower error rates than NOR and vice versa, but in general, NOR is the more expensive technology, exactly because you can't pack its cells as tightly.

This tight packing comes with the downside of neighboring bits having effects on each other.

Also, it leads to a different "business model", where in NAND you go all in on packing bits tightly, make the floating gate charges smaller and compensating the resulting higher error rates due to crosstalk/-bleeding and easier bit flips with ECC.

NOR, however isn't "perfect". I'd expect that in any memory of significant size, you'll definitely want a flash transaction layer that adds error correction! Modern codes for flash memory are very capable and high-rate (in the channel-coding sense: you lose very little usable memory for a lot of error correction ability), so only when design constraints like very low latency force you to abandon these benefits would you not do ECC.

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    \$\begingroup\$ Programs can be executed directly from NOR flash, which is impossible in the presence of bad blocks. \$\endgroup\$ Jul 29, 2021 at 14:07
  • \$\begingroup\$ @user253751 that statement is true, but it's also true for NAND flash. NOR or NAND flash makes no difference there. \$\endgroup\$ Jul 29, 2021 at 20:36
  • \$\begingroup\$ Are there systems that execute directly from NAND flash? \$\endgroup\$ Jul 30, 2021 at 8:41
  • \$\begingroup\$ yes, as much as there are system that execute directly from NOR flash. \$\endgroup\$ Jul 30, 2021 at 10:15
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    \$\begingroup\$ An interesting addition. NAND flash (as used in mass storage) is usually (consumer grade anyway) MLC so there are multiple voltage levels that may be stored unlike NOR where they are single level (either high or low). NAND is available in SLC but at a price. The geometries are also limited for NOR. The consensus a few years ago was that 65nm was the smallest feature size that would really be suitable (apart from the tunnel oxide which is typically 5nm to 15nm). \$\endgroup\$ Jul 30, 2021 at 10:55
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The reason a flash memory stick or solid state disk has no bad blocks is that your computer doesn't get to see them.

A device can be manufactured with a number of spare blocks, and a controller chip that provides the USB or SATA interface. If the controller sees an unreliable block, it can mark it as bad, and redirect any reads or writes to one of the spare blocks. Unlike a spinning hard disk, this causes no significant increase in latency. The computer never directly accesses the storage, and so never even sees the bad block.

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    \$\begingroup\$ This only covers bad blocks as manufacturing failures, which is not to do with the error rate the OP asks about. That's about blocks that fail over time. The controller can't hide that from the filing system. A section of a file will have disappeared. \$\endgroup\$
    – TonyM
    Jul 29, 2021 at 14:00
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    \$\begingroup\$ Programs can be executed directly from NOR flash, which is impossible in the presence of bad blocks. \$\endgroup\$ Jul 29, 2021 at 14:07
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    \$\begingroup\$ We also need to keep in mind the the term bad block, at least as is used with NAND Flash memories I've used, does not mean that the entire block is bad, but only that one or a handful of bits may be bad. With proper ECC techniques, such as Reed-Solomon encoding, one can use "bad blocks" as if they were error free. Of course, you would need to ensure that the number and organization of the bad bits does not exceed what the ECC scheme can correct for. \$\endgroup\$
    – SteveSh
    Jul 29, 2021 at 15:55
  • \$\begingroup\$ @TonyM If the flash controller detects failing blocks, moves the data into a non-failing block and remaps, the filesystem will never see the failure. \$\endgroup\$
    – wizzwizz4
    Jul 29, 2021 at 21:07
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    \$\begingroup\$ @wizzwizz4, your description is only of a powered-on controller and one that can examine blocks and copy them while their data can still be retrieved. Instead, what about, for example, a unpowered USB stick that has large bit failures over time through heat or other harsh environmentals, causing block failures. When that's powered on, block data cannot be recovered and so not moved to a new block. Same for a portable HDD that's undergone mechanical shock, heat or magnetic interference. All these things go on and these are only a few examples. \$\endgroup\$
    – TonyM
    Jul 29, 2021 at 21:54
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Using ECC with NOR flash is not unheard of. For example STM32H7 series of microcontrollers has error correction for its flash memory.

There is a significant difference in how NOR and NAND flash are used. NOR flash chips are small and are used to store firmware images, which are rarely updated and are verified in full after update. In comparison, NAND flash is common for storing user data which has much larger amount of write cycles.

When NOR flash is used for storing frequently changing data, it is usually combined with a flash-aware filesystem that has its own checksum and potentially error correction mechanisms.

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