I'd like to build a VHDL model of the propagation delays on my board. For unidirectional signals, that is easy:
u1_pinb3 <= transport u2_pin3 after 10 ps; -- todo replace by actual delay from board model u2_pin4 <= transport u1_pinb4 after 10 ps;
However, for bidirectional signals that would obviously create a loop:
u1_pinb5 <= transport u2_pin5 after 10 ps; u2_pin5 <= transport u1_pinb5 after 10 ps;
If I have simulation models of two components that talk to each other over a bidirectional bus, can I somehow generate a full system simulation that lets me inspect bus turnaround?