Modeling bidirectional propagation delays

Question

I'd like to build a VHDL model of the propagation delays on my board. For unidirectional signals, that is easy:

u1_pinb3 <= transport u2_pin3 after 10 ps;     -- todo replace by actual delay from board model
u2_pin4 <= transport u1_pinb4 after 10 ps;

However, for bidirectional signals that would obviously create a loop:

u1_pinb5 <= transport u2_pin5 after 10 ps;
u2_pin5 <= transport u1_pinb5 after 10 ps;

If I have simulation models of two components that talk to each other over a bidirectional bus, can I somehow generate a full system simulation that lets me inspect bus turnaround?

Answer 1

Typically inout ports have controls that enable the drivers.

u1_pinb5 <= u2_pin5 after 10 ps when Control = '1' else 'Z' after 10 ps ;

Answer 2

If you "know" when each chip is driving the bus you could try something like:

   p_delays : process(ic1_drive, ic2_drive, ic1_pin_io, ic2_pin_io)
   begin
     ic1_pin_io <= transport 'Z' after (12 ps);
     ic2_pin_io <= transport 'Z' after (13 ps);

     if(ic1_drive) then
       ic2_pin_io <= transport ic1_pin_io after 9 ps;
       ic1_pin_io <= transport 'Z' after 12 ps;
     end if;
     if(ic2_drive) then
       ic1_pin_io <= transport ic2_pin_io after 11 ps;
       ic2_pin_io <= transport 'Z' after 13 ps;
     end if;
   end process p_delays;

With:

• U1 having: any-to-data delay of 10 ps, data-to-Z delay of 13 ps
• U2 having: any-to-data delay of 11 ps, data-to-Z delay of 12 ps

To create ic1_drive and ic2_drive the test bench must look at the control signals in the transaction, and determine what is happening (this may be non trivial).

Answer 3

Maybe, but it’s not trivial. I believe it is better to model the transmission line with the Dk or ps/mm, and all impedances. Then with path length the trace ringing from risetime and return loss or impedance mismatch with an understanding of the metastable margins for synchronous transfer and voltage margins with component tolerances , path skew etc, are more useful.

Verification requires adding mismatch tolerances to impedance and path skew to determine the timing margin variations with temperature and supply tolerances.

https://www.researchgate.net/publication/224238992_Formal_verification_of_timed_VHDL_programs

If you can imagine it, you can synthesize it!

Notice what happens when you use 3V logic ungerminated with a short ohm strip loaded by input capacitance at 500 MHz or any speed for that matter if the risetime is faster than delay time.