I want to use a self written Python, Bash or C++ program to communicate with an FPGA using its JTAG port. This would be somewhat similar to how we write programs to communicate using UART. Now the problem is that, to my knowledge, none of the vendors like Intel/Altera and Microsemi provide drivers that can be used to make simple read/write access to FPGA using their FPGA programmers in a custom application. Here I am talking about things like USB Byte Blaster and Flash Pro series programmers. The API for these is not in public domain and no one has reverse engineered them as well.

Now does there exist a "general purpose JTAG communicator" which I can connect into my PC's USB port and just use a basic API to send read/write requests to it to be executed on the FPGA's JTAG port? I do not know if something like this exists.

Note: I do not intend to use the JTAG device for boundary scan. FPGAs usually contain hard IP that can be used in user designs whereby, the user design is able to reach to JTAG requests. In this way, it send data out onto JTAG and read data being sent using JTAG. Intel/Altera has "Virtual JTAG" IP while Microsemi has "UJTAG" IP. The problem is that Microsemi does not provide any support in anyway, to help people communicate with the design using UJTAG IP. This is true for all new devices. Only in very old devices is there a very limited support and we have to write STAPL script to make it work!

  • \$\begingroup\$ Often when people say JTAG, they mean ICE/SWD, which is cpu specific and sometimes proprietary. Yes generic JTAG probes exist, but boundary scan is not usually what developers are looking for. \$\endgroup\$
    – crasic
    Jul 31 at 13:32
  • 1
    \$\begingroup\$ Segger's J-Link has a DLL with a documented API and examples for Python, C#, VB.NET, etc. segger.com/products/debug-probes/j-link/technology/j-link-sdk \$\endgroup\$
    – brhans
    Jul 31 at 14:03
  • \$\begingroup\$ The USB-device is not your problem, there are many chips for this, e.g. FT2232. But without the reverse engineered protocol necessary for your specific IC it's impossible to do anything useful with it. \$\endgroup\$
    – asdfex
    Jul 31 at 14:42
  • \$\begingroup\$ I want to save on having to use extra pins for serial comms. I just need something that can be sent commands to wiggle the TCK, TDI, TDO e.t.c pins on JTAG at will and the rest of the problems will be solved actually. I have asked Microsemi for drivers many times but they are just not open about it. \$\endgroup\$
    – quantum231
    Jul 31 at 18:32

The Virtual JTAG User Guide notes that

The Virtual JTAG Intel FPGA IP core Tcl API requires an Intel programming cable.Designs that use a custom controller to drive the JTAG chain directly must issue thecorrect JTAG IR/DR transactions to target the Virtual JTAG Intel FPGA IP coreinstances. The address values and register length information for each Virtual JTAGIntel FPGA IP core instance are provided in the compilation reports.

So this seems to be a supported interface on Intel FPGAs at least, I'd expect the same on Xilinx.

There is a wide range of JTAG adapters that are supported through OpenOCD, and the commands to send are documented -- likely there are two IR values, one of which connects the virtual IR to DR, and one that connects the virtual DR to DR. The length of the virtual IR and supported values, as well as lengths of the virtual DR for various settings of the virtual IR depends on your design, that's why it refers you to the compilation report.

  • \$\begingroup\$ The problem I have is that Microsemi does not provide anything along these lines. There us no "system console" that comes with thier Libero SoC like we have with Intel Quartus. \$\endgroup\$
    – quantum231
    Aug 3 at 13:48

The way I understand the UJTAG documentation, the JTAG protocol is visible to the UJTAG block completely, and the normal JTAG block ignores any IR values from 16 to 127.

So, you'd define IR values in that range, and then connect your DR registers between UTDI and UTDO and react to capture and update strobes while UIR[7:0] is equal to the value you want. On the JTAG side, you just update the IR to your value, and then shift data through the DR chain.

  • \$\begingroup\$ The AC227 describes the UJTAG. The problem is that I have no way to make the FlashPro programmer do something on its JTAG. It always takes commands from Microsemi applications like Libero. No way to control it directly. \$\endgroup\$
    – quantum231
    Aug 3 at 23:43
  • \$\begingroup\$ @quantum231, then just use any other adapter or see if you can get a version of OpenOCD that supports the FlashPro (these exist). \$\endgroup\$ Aug 4 at 9:44

First of all, understand that JTAG is only a glorified SPI with an additional mode set pin. There is a communication framework (the mode set) and then everything else from boundary scan, to programming to runtime communication is ran on that framework (something like a communication profile)

In short, it's mostly a software and documentation issue: boundary scan is standard and documented, the programming protocols are mostly proprietary and sometime are documented, the internal IP core communication is often a black box only known to the manufacturer.

So, doing an universal JTAG adapter is quite easy but the software to drive it need to be developed case by case.

Also many MCUs have a 'fake' JTAG which often doesn't even handle bypass and daisy chain, be careful with these.


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